= +5 V, AGND = DGND = 0 V, REF IN = +2.5 V. All specifications T
MIN
to T
MAX
unless
otherwise noted.)
B
Versions
S
Version
Units
Test Conditions/Comments
70
–80
–80
–80
–80
12
12
±
1
±
1
±
3
±
4
±
3
±
4
70
–80
–80
–80
–80
12
12
±
1/2
±
1
±
1.5
±
3
±
1.5
±
2
70
–80
–80
–80
–80
12
12
±
1
±
1
±
3
±
4
±
3
±
4
dB min
dB max
dB max
dB max
dB max
Bits
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
f
IN
= 10 kHz Sine Wave, f
SAMPLE
= 117 kHz
f
IN
= 10 kHz Sine Wave, f
SAMPLE
= 117 kHz
f
IN
= 10 kHz Sine Wave, f
SAMPLE
= 117 kHz
fa = 9 kHz, fb
=
9.5 kHz, f
SAMPLE
= 117 kHz
±
10
16
±
2.5
4
0 to +5
9
0 to +2.5
500
2.375/2.625
2
10
2.4
0.8
±
10
10
4.0
0.4
±
10
16
±
2.5
4
0 to +5
9
0 to +2.5
500
2.375/2.625
2
10
2.4
0.8
±
10
10
4.0
0.4
2s Complement
Straight (Natural) Binary
±
10
16
±
2.5
4
0 to +5
9
0 to +2.5
500
2.375/2.625
10
10
2.4
0.8
±
10
10
4.0
0.4
Volts
kΩ min
Volts
kΩ min
Volts
kΩ min
Volts
nA max
V min/V max 2.5 V
±
5%
µA
max
pF max
V min
V max
µA
max
pF max
V min
V max
V
DD
= 5 V
±
5%
V
DD
= 5 V
±
5%
V
IN
= 0 V to V
DD
I
SOURCE
= 200
µA
I
SINK
= 1.6 mA
6
1.5
+5
9
45
6
1.5
+5
9
45
6
1.5
+5
9
45
µs
max
µs
max
V nom
mA max
mW max
±
5% for Specified Performance
Typically 25 mW
NOTES
1
Temperature Ranges are as follows: A, B Versions: –40°C to +85°C, S Version: –55°C to +125°C.
2
See Terminology.
3
Sample tested @ +25°C to ensure compliance.
Specifications subject to change without notice.
–2–
REV. E
AD7893
TIMING CHARACTERISTICS
1, 2
(V
Parameter
t
1
t
2
t
3
t
4 3
t
5 4
A, B
Versions
50
60
30
50
10
100
50
70
40
60
10
100
DD
= +5 V, AGND = DGND = 0 V, REF IN = +2.5 V)
Units
ns min
ns min
ns min
ns max
ns min
ns max
Test Conditions/Comments
CONVST
Pulse Width
SCLK High Pulse Width
SCLK Low Pulse Width
SCLK Rising Edge to Data Valid Delay
Bus Relinquish Time after Falling Edge of SCLK
S
Version
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6 V.
2
See Figure 5.
3
Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
5
, quoted in the timing characteristics is the true bus relinquish time
of the part and, as such, is independent of external bus loading capacitances.
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25°C unless otherwise noted)
V
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
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FPGA/CPLD
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