M7AFS1500-1FGG676 datasheet, PDF

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M7AFS1500-1FGG676: DescriptionField Programmable Gate Array, 1500000 Gates, CMOS, PBGA676, 1 MM PITCH, GREEN, FBGA-676; CategoryProgrammable logic devices Programmable logic; File Size3MB，272 Pages; ManufacturerActel; Websitehttp://www.actel.com/; Environmental Compliance

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M7AFS1500-1FGG676 Overview

Field Programmable Gate Array, 1500000 Gates, CMOS, PBGA676, 1 MM PITCH, GREEN, FBGA-676

M7AFS1500-1FGG676 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
package instruction	1 MM PITCH, GREEN, FBGA-676
Reach Compliance Code	compliant
JESD-30 code	S-PBGA-B676
JESD-609 code	e1
length	23 mm
Humidity sensitivity level	3
Equivalent number of gates	1500000
Number of terminals	676
Maximum operating temperature	70 °C
Minimum operating temperature
organize	1500000 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	250
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	2.44 mm
Maximum supply voltage	1.575 V
Minimum supply voltage	1.425 V
Nominal supply voltage	1.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
width	23 mm
Base Number Matches	1

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Advanced v0.8

Fusion Family of Mixed-Signal Flash FPGAs

with Optional Soft ARM Support

Features and Benefits

High-Performance Reprogrammable Flash Technology

•

Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process

Nonvolatile, Retains Program when Powered Off

Live at Power-Up (LAPU) Single-Chip Solution

350 MHz System Performance

User Flash Memory – 2 Mbits to 8 Mbits

– Configurable 8-, 16-, or 32-Bit Datapath

– 10 ns Access in Read-Ahead Mode

1 kbit of Additional FlashROM

Up to 12-Bit Resolution and up to 600 ksps

Internal 2.56 V or External Reference Voltage

ADC: Up to 30 Scalable Analog Input Channels

High-Voltage Input Tolerance: ±12 V

Current Monitor and Temperature Monitor Blocks

Up to 10 MOSFET Gate Driver Outputs

– P- and N-Channel Power MOSFET Support

– Programmable 1, 3, 10, 30 µA and 25 mA Drive Strengths

Internal 100 MHz RC Oscillator (accurate to 1%)

Crystal Oscillator Support (32 kHz to 20 MHz)

Programmable Real-Time Counter (RTC)

6 Clock Conditioning Circuits (CCCs) with 1 or 2 Integrated PLLs

– Phase Shift, Multiply/Divide, and Delay Capabilities

– Frequency: Input 1.5–350 MHz, Output 0.75–350 MHz

Low Power Consumption

•

Single 3.3 V Power Supply with On-Chip 1.5 V Regulator

Sleep and Standby Low Power Modes

Secure ISP with 128-Bit AES via JTAG

FlashLock

to Secure FPGA Contents

1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

Bank-Selectable I/O Voltages – Up to 5 Banks per Chip

Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V /1.8 V /

1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS 2.5 V / 5.0 V Input

Differential I/O Standards: LVPECL, LVDS, BLVDS, and M-LVDS

– Built-In I/O Registers

– 700 Mbps DDR Operation

Hot-Swappable I/Os

Programmable Output Slew Rate, Drive Strength, and Weak

Pull-Up/Down Resistor

Pin-Compatible Packages across the Fusion Family

Variable-Aspect-Ratio 4,608-Bit SRAM Blocks (×1, ×2, ×4, ×9,

and ×18 organizations available)

True Dual-Port SRAM (except ×18)

Programmable Embedded FIFO Control Logic

CortexM1(without debug), CoreMP7Sd (with debug) and

CoreMP7S (without debug)

In-System Programming (ISP) and Security

Advanced Digital I/O

Embedded Flash Memory

•

Integrated A/D Converter (ADC) and Analog I/O

•

SRAMs and FIFOs

On-Chip Clocking Support

•

Soft ARM7™ Core Support in M7 and M1 Fusion Devices

Table 1 •

Fusion Family

AFS090

CoreMP7

Cortex-M1

System Gates

90,000

2,304

Yes

Tiles (D-flip-flops)

Secure (AES) ISP

PLLs

Globals

Flash Memory Blocks (2 Mbits)

Total Flash Memory Bits

M1AFS250

250,000

6,144

Yes

114

AFS250

AFS600

M7AFS600

M1AFS600

600,000

13,824

Yes

108

172

M1AFS1500

1,500,000

38,400

Yes

270

252

AFS1500

Fusion Devices

ARM-Enabled

Fusion Devices

General

Information

Memory

FlashROM Bits

RAM Blocks (4,608 bits)

RAM kbits

Analog Quads

Analog Input Channels

Gate Driver Outputs

I/O Banks (+ JTAG)

Maximum Digital I/Os

Analog I/Os

Analog and I/Os

Notes:

1. Refer to the

CoreMP7

datasheet for more information.

2. Refer to the

Cortex-M1

product brief for more information.

June 2007

See the Actel website for the latest version of the datasheet.

Fusion Family of Mixed-Signal Flash FPGAs

Table of Contents

Introduction and Overview

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Unprecedented Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

Device Architecture

Fusion Stack Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Core Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

Clocking Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

Real-Time Counter System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31

Embedded Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37

Analog Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-71

Analog Configuration MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-94

User I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-100

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-184

Software Tools and Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-187

DC and Power Characteristics

General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25

Package Pin Assignments

108-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

180-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

256-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

484-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20

676-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

Export Administration Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

A d va n ce d v 0 . 8

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