Advanced v0.8
Fusion Family of Mixed-Signal Flash FPGAs
with Optional Soft ARM Support
Features and Benefits
High-Performance Reprogrammable Flash Technology
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Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process
Nonvolatile, Retains Program when Powered Off
Live at Power-Up (LAPU) Single-Chip Solution
350 MHz System Performance
User Flash Memory – 2 Mbits to 8 Mbits
– Configurable 8-, 16-, or 32-Bit Datapath
– 10 ns Access in Read-Ahead Mode
1 kbit of Additional FlashROM
Up to 12-Bit Resolution and up to 600 ksps
Internal 2.56 V or External Reference Voltage
ADC: Up to 30 Scalable Analog Input Channels
High-Voltage Input Tolerance: ±12 V
Current Monitor and Temperature Monitor Blocks
Up to 10 MOSFET Gate Driver Outputs
– P- and N-Channel Power MOSFET Support
– Programmable 1, 3, 10, 30 µA and 25 mA Drive Strengths
Internal 100 MHz RC Oscillator (accurate to 1%)
Crystal Oscillator Support (32 kHz to 20 MHz)
Programmable Real-Time Counter (RTC)
6 Clock Conditioning Circuits (CCCs) with 1 or 2 Integrated PLLs
– Phase Shift, Multiply/Divide, and Delay Capabilities
– Frequency: Input 1.5–350 MHz, Output 0.75–350 MHz
®
®
Low Power Consumption
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Single 3.3 V Power Supply with On-Chip 1.5 V Regulator
Sleep and Standby Low Power Modes
Secure ISP with 128-Bit AES via JTAG
FlashLock
®
to Secure FPGA Contents
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages – Up to 5 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V /1.8 V /
1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS 2.5 V / 5.0 V Input
Differential I/O Standards: LVPECL, LVDS, BLVDS, and M-LVDS
– Built-In I/O Registers
– 700 Mbps DDR Operation
Hot-Swappable I/Os
Programmable Output Slew Rate, Drive Strength, and Weak
Pull-Up/Down Resistor
Pin-Compatible Packages across the Fusion Family
Variable-Aspect-Ratio 4,608-Bit SRAM Blocks (×1, ×2, ×4, ×9,
and ×18 organizations available)
True Dual-Port SRAM (except ×18)
Programmable Embedded FIFO Control Logic
CortexM1(without debug), CoreMP7Sd (with debug) and
CoreMP7S (without debug)
In-System Programming (ISP) and Security
Advanced Digital I/O
Embedded Flash Memory
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Integrated A/D Converter (ADC) and Analog I/O
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SRAMs and FIFOs
On-Chip Clocking Support
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Soft ARM7™ Core Support in M7 and M1 Fusion Devices
Table 1 •
Fusion Family
AFS090
CoreMP7
1
Cortex-M1
2
System Gates
90,000
2,304
Yes
1
18
1
2M
1k
6
27
5
15
5
4
75
20
Tiles (D-flip-flops)
Secure (AES) ISP
PLLs
Globals
Flash Memory Blocks (2 Mbits)
Total Flash Memory Bits
M1AFS250
250,000
6,144
Yes
1
18
1
2M
1k
8
36
6
18
6
4
114
24
AFS250
AFS600
M7AFS600
M1AFS600
600,000
13,824
Yes
2
18
2
4M
1k
24
108
10
30
10
5
172
40
M1AFS1500
1,500,000
38,400
Yes
2
18
4
8M
1k
60
270
10
30
10
5
252
40
AFS1500
Fusion Devices
ARM-Enabled
Fusion Devices
General
Information
Memory
FlashROM Bits
RAM Blocks (4,608 bits)
RAM kbits
Analog Quads
Analog Input Channels
Gate Driver Outputs
I/O Banks (+ JTAG)
Maximum Digital I/Os
Analog I/Os
Analog and I/Os
Notes:
1. Refer to the
CoreMP7
datasheet for more information.
2. Refer to the
Cortex-M1
product brief for more information.
June 2007
© 2007 Actel Corporation
i
See the Actel website for the latest version of the datasheet.
Fusion Family of Mixed-Signal Flash FPGAs
Bank 0
Bank 1
CCC
SRAM Block
4,608-Bit Dual-Port SRAM
or FIFO Block
OSC
I/Os
CCC/PLL
VersaTile
Bank 2
Bank 4
ISP AES
Decryption
User Nonvolatile
FlashROM
Charge Pumps
SRAM Block
4,608-Bit Dual-Port SRAM
or FIFO Block
Flash Memory Blocks
ADC
Flash Memory Blocks
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
CCC
Bank 3
Figure 1 •
Fusion Device Architecture Overview (AFS600)
Package I/Os: Single-/Double-Ended (Analog)
Fusion Devices
ARM-Enabled Devices
QN108
QN180
PQ208
FG256
FG484
FG676
75/22 (20)
CoreMP7
Cortex-M1
37/9 (16)
60/16 (20)
65/15 (24)
93/26 (24)
114/37 (24)
95/46 (40)
119/58 (40)
172/86 (40)
119/58 (40)
223/109 (40)
252/126 (40)
M1AFS250
AFS090
AFS250
AFS600
M7AFS600
M1AFS600
M1AFS1500
AFS1500
Note:
All devices in the same package are pin compatible with the exception of the PQ208 package (AFS250 and AFS600).
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A d v a n c e d v 0 .8
Fusion Family of Mixed-Signal Flash FPGAs
Product Ordering Codes
M7AFS600
_
1
FG
G
256
I
Application (ambient temperature range)
Blank = Commercial (0 to +70°C)
I = Industrial (–40 to +85°C)
PP = Pre-Production
ES = Engineering Silicon (room temperature only)
Package Lead Count
Lead-Free Packaging Options
Blank = Standard Packaging
G = RoHS-Compliant (green) Packaging
Package Type
QN = Quad Flat No Lead (0.5 mm pitch)
PQ = Plastic Quad Flat Pack (0.5 mm pitch)
FG = Fine Pitch Ball Grid Array (1.0 mm pitch)
Speed Grade
F = 20% Slower than Standard
Blank = Standard
1 = 15% Faster than Standard
2 = 25% Faster than Standard
Part Number
Fusion Devices
AFS090 = 90,000 System Gates
AFS250 = 250,000 System Gates
AFS600 = 600,000 System Gates
AFS1500 = 1,500,000 System Gates
ARM-Enabled Fusion Devices
M7AFS600
M1AFS250
M1AFS600
M1AFS1500
=
=
=
=
600,000 System Gates
250,000 System Gates
600,000 System Gates
1,500,000 System Gates
Notes:
1. DC and switching characteristics for –F speed grade targets are based only on simulation. The characteristics provided for the –F
speed grade are subject to change after establishing FPGA specifications. Some restrictions might be added and will be reflected in
future revisions of this document. The –F speed grade is only supported in the commercial temperature range.
2. Quad Flat No Lead packages are only offered as RoHS compliant, QNG.
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Fusion Family of Mixed-Signal Flash FPGAs
Temperature Grade Offerings
Fusion Devices
ARM-Enabled Devices
QN108
QN180
PQ208
FG256
FG484
FG676
Notes:
1. C = Commercial Temperature Range: 0°C to 70°C Ambient
2. I = Industrial Temperature Range: –40°C to 85°C Ambient
CoreMP7
Cortex-M1
C, I
C, I
–
C, I
–
–
M1AFS250
–
C, I
C, I
C, I
–
–
AFS090
AFS250
AFS600
M7AFS600
M1AFS600
–
–
C, I
C, I
C, I
–
M1AFS1500
–
–
–
C, I
C, I
C, I
AFS1500
Speed Grade and Temperature Grade Matrix
–F
1
C
2
I
3
Notes:
1. DC and switching characteristics for –F speed grade targets are based only on simulation. The characteristics provided for the –F speed
grade are subject to change after establishing FPGA specifications. Some restrictions might be added and will be reflected in future
revisions of this document. The –F speed grade is only supported in the commercial temperature range.
2. C = Commercial Temperature Range: 0°C to 70°C Ambient
3. I = Industrial Temperature Range: –40°C to 85°C Ambient
✓
–
Std.
✓
✓
–1
✓
✓
–2
✓
✓
Contact your local Actel representative for device availability (http://www.actel.com/contact/offices/index.html).
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A d v a n c e d v 0 .8
Fusion Family of Mixed-Signal Flash FPGAs
Table of Contents
Introduction and Overview
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Unprecedented Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Device Architecture
Fusion Stack Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Core Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Clocking Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
Real-Time Counter System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31
Embedded Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37
Analog Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-71
Analog Configuration MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-94
User I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-100
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-184
Software Tools and Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-187
DC and Power Characteristics
General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
Package Pin Assignments
108-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
180-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
256-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
484-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
676-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
Export Administration Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
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