EQVA12A1C2H-35.328M datasheet, PDF

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EQVA12A1C2H-35.328M: DescriptionCMOS, Voltage Controlled Quartz Crystal Clock Oscillators VCXO LVCMOS (CMOS) 2.5Vdc 6 Pad 5.0mm x 7.0mm Ceramic Surface Mount (SMD) Voltage Controlled Quartz Crystal Clock Oscillators VCXO LVCMOS (CMOS) 2.5Vdc 6 Pad 5.0mm x 7.0mm Ceramic Surface Mount (SMD); CategoryPassive components oscillator; File Size958KB，7 Pages; ManufacturerECLIPTEK; Websitehttp://www.ecliptek.com; Environmental Compliance

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EQVA12A1C2H-35.328M Overview

CMOS, Voltage Controlled Quartz Crystal Clock Oscillators VCXO LVCMOS (CMOS) 2.5Vdc 6 Pad 5.0mm x 7.0mm Ceramic Surface Mount (SMD) Voltage Controlled Quartz Crystal Clock Oscillators VCXO LVCMOS (CMOS) 2.5Vdc 6 Pad 5.0mm x 7.0mm Ceramic Surface Mount (SMD)

EQVA12A1C2H-35.328M Parametric

Parameter Name	Attribute value
Brand Name	Ecliptek
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Parts packaging code	SMD 5.0mm x 7.0mm
package instruction	SMD, 6 PIN
Contacts	6
Manufacturer packaging code	SMD 5.0mm x 7.0mm
Reach Compliance Code	unknown
Other features	ENABLE/DISABLE FUNCTION; BULK; TAPE
Maximum control voltage	2.75 V
Minimum control voltage	0.25 V
maximum descent time	3 ns
Frequency Adjustment - Mechanical	NO
Frequency offset/pull rate	30 ppm
frequency stability	50%
JESD-609 code	e4
linearity	10%
Installation features	SURFACE MOUNT
Nominal operating frequency	35.328 MHz
Maximum operating temperature	70 °C
Minimum operating temperature
Oscillator type	CMOS
Output load	15 pF
physical size	7.0mm x 5.0mm x 1.8mm
longest rise time	3 ns
Maximum supply voltage	2.625 V
Minimum supply voltage	2.375 V
Nominal supply voltage	2.5 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	GOLD (39) OVER NICKEL (350)
Base Number Matches	1

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EQVA12A1C2H-35.328M

REGULATORY COMPLIANCE

2011/65 +

2015/863

(Data Sheet downloaded on Sep 5, 2020)

191 SVHC

ITEM DESCRIPTION

Voltage Controlled Quartz Crystal Clock Oscillators VCXO LVCMOS (CMOS) 2.5Vdc 6 Pad 5.0mm x 7.0mm Ceramic Surface

Mount (SMD) 35.328MHz ±50ppm 0°C to +70°C

ELECTRICAL SPECIFICATIONS

Nominal Frequency

Frequency Tolerance/Stability

Aging at 25°C

Operating Temperature Range

Supply Voltage

Input Current

Output Voltage Logic High (Voh)

Output Voltage Logic Low (Vol)

Rise/Fall Time

Duty Cycle

Load Drive Capability

Output Logic Type

Absolute Pull Range

35.328MHz

±50ppm Maximum (Inclusive of all conditions: Calibration Tolerance (at 25°C), Frequency Stability over the Operating

Temperature Range, Supply Voltage Change and Output Load Change)

±2ppm Maximum First Year, ±10ppm/10 Years Maximum

0°C to +70°C

2.5Vdc ±5%

20mA Maximum (Unloaded)

90% of Vdd Minimum (IOH = -4mA)

10% of Vdd Maximum (IOL = +4mA)

3nSec Maximum (Measured at 10% to 90% of Waveform)

50 ±5(%) (Measured at 50% of Waveform)

15pF Maximum

CMOS

±30ppm Minimum (Inclusive of all conditions: Calibration Tolerance (at 25°C), Frequency Stability over the Operating

Temperature Range, Supply Voltage Change, Output Load Change, Shock, Vibration, and 10 Year Aging over the

Control Voltage (Vc))

0.2Vdc to 2.3Vdc (Test Condition for APR)

0.0Vdc to Vdd +0.25Vdc

5% Typical, 10% Maximum

Positive Tranfer Characteristic

10kHz Minimum (Measured at -3dB, Vc = 1.25Vdc)

500kOhms Minimum

10µA Maximum

-64dBc/Hz at 10Hz offset; -96dBc/Hz at 100Hz offset; -124dBc/Hz at 1kHz offset; -131dBc/Hz at 10kHz offset; -

132dBc/Hz at 100kHz offset; -149dBc/Hz at 1MHz offset; -157dBc/Hz at 10MHz offset; -159dBc/Hz at 20MHz offset (All

Values are Typical)

Output Enable (OE)

90% of Vdd Minimum or No Connect to Enable Output

10% of Vdd Maximum to Disable Output (High Impedance)

100nSec Maximum

50nSec Maximum

15mA Maximum (Without Load (Pin 2 = Ground))

1.5pSec Maximum (Fj=12kHz to 20MHz (Random))

0.2pSec Typical

2pSec Typical

3pSec Maximum

30pSec Maximum

10mSec Maximum

Control Voltage

Control Voltage Range

Linearity

Transfer Function

Modulation Bandwidth

Input Impedance

Input Leakage Current

Phase Noise

Output Control Function

Output Control Input Voltage Logic

High (Vih)

Output Control Input Voltage Logic

Low (Vil)

Output Enable Time

Output Disable Time

Output Enable Current

RMS Phase Jitter

Period Jitter (Deterministic)

Period Jitter (Random)

Period Jitter (RMS)

Period Jitter (pk-pk)

Start Up Time

www.ecliptek.com | Specification Subject to Change Without Notice | Revision B 01/18/2019 | Page 1 of 7

Ecliptek, LLC

5458 Louie Lane, Reno, NV 89511

1-800-ECLIPTEK or 714.433.1200

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