U62H64SA
Automotive Fast 8K x 8 SRAM
Features
Description
The U62H64SA is a static RAM
manufactured using a CMOS pro-
cess technology with the following
operating modes:
- Read
- Standby
- Write
- Data Retention
The memory array is based on a
6-transistor cell.
The circuit is activated by the rising
edge of E2 (at E1 = L), or the falling
edge of E1 (at E2 = H). The
address and control inputs open
simultaneously.
According to the information of W
and G, the data inputs, or outputs,
are active. During the active state
(E1 = L and E2 = H), each address
change leads to a new Read or
Write cycle. In a Read cycle, the
data outputs are activated by the
falling edge of G, afterwards the
data word read will be available at
the outputs DQ0 - DQ7. After the
address change, the data outputs
go High-Z until the new read infor-
mation is available. The data out-
puts have no preferred state. If the
memory is driven by CMOS levels
in the active state, and if there is no
change of the address, data input
and control signals W or G, the ope-
rating current (at I
O
= 0 mA) drops to
the value of the operating current in
the Standby mode. The Read cycle
is finished by the falling edge of E2
or W, or by the rising edge of E1,
respectively.
Data retention is guaranteed down
to 2 V.
With the exception of E1 and E2, all
inputs consist of NOR gates, so that
no pull-up/pull-down resistors are
required. This gate circuit allows to
achieve low power standby require-
ments by activation with TTL-levels
too.
F
Fast 8192 x 8 bit static CMOS RAM
F
35 ns Access Time
F
Bidirectional data inputs and data
outputs
F
Three-state outputs
F
Data retention current at 3 V:
< 50
µA
F
Standby current < 100
µA
F
TTL/CMOS-compatible
F
Automatic reduction of power
F
F
F
F
F
F
dissipation in long Read or Write
cycles
Power supply voltage 5 V
Operating temperature range
-40 to 125
°C
Quality assessment according to
CECC 90000, CECC 90100 and
CECC 90111
ESD protection > 2000 V
(MIL STD 883C M3015.7)
Latch-up immunity > 200 mA
Package: SOP28 (300 mil)
Pin Configuration
n.c.
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
W (WE)
E2 (CE2)
A8
A9
A11
G (OE)
A10
E1 (CE1)
DQ7
DQ6
DQ5
DQ4
DQ3
Pin Description
Signal Name
A0 - A12
DQ0 - DQ7
E1
E2
G
W
VCC
VSS
n.c.
Signal Description
Address Inputs
Data In/Out
Chip Enable 1
Chip Enable 2
Output Enable
Write Enable
Power Supply Voltage
Ground
not connected
SOP
Top View
December 12, 1997
1
U62H64SA
Block Diagram
A6
A7
A8
A9
A10
A11
A12
A0
A1
A2
A3
A4
A5
Row Decoder
Row Address
Inputs
Memory Cell
Array
128 Rows
64 x 8 Columns
Column Address
Inputs
Column Decoder
DQ0
Bidirectional Data I/O
Sense Amplifier/
Write Control Logic
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Address
Change
Detector
Clock
Generator
E2
E1
V
CC
V
SS
W
G
Truth Table
Operating Mode
Standby/not
selected
Internal Read
Read
Write
* H or L
E1
*
H
L
L
L
E2
L
*
H
H
H
W
*
*
H
H
L
G
*
*
H
L
*
DQ0 - DQ7
High-Z
High-Z
High-Z
Data Outputs Low-Z
Data Inputs High-Z
Characteristics
All voltages are referenced to V
SS
= 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of
≤
5 ns, measured between 10 % and 90 % of V
I
, as well as
input levels of V
IL
= 0 V and V
IH
= 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the t
dis
-times and t
en
-times, in which cases transition is measured
±
200 mV from steady-state voltage.
Maximum Ratings
Power Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Storage Temperature
Output Short-Circuit Current
at V
CC
= 5 V and V
O
= 0 V
*
Symbol
V
CC
V
I
V
O
T
a
T
stg
|I
OS
|
Min.
-0.3
-0.3
-0.3
-40
-65
Max.
7
V
CC
+ 0.5
V
CC
+ 0.5
125
150
200
Unit
V
V
V
°C
°C
mA
* Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 s.
2
December 12, 1997
U62H64SA
Recommended
Operating Conditions
Power Supply Voltage
Data Retention Voltage
Input Low Voltage *
Input High Voltage
Symbol
V
CC
V
CC(DR)
V
IL
V
IH
Conditions
Min.
4.5
2.0
-0.3
2.2
Max.
5.5
Unit
V
V
V
V
-
0.8
V
CC
+0.3
* -2 V at Pulse Width 10 ns or -1 V at Pulse Width 50 ns
Electrical Characteristics
Supply Current - Operating Mode
Symbol
I
CC(OP)
V
CC
V
IL
V
IH
t
cW
Conditions
= 5.5 V
= 0.8 V
= 2.2 V
= 35 ns
= 5.5 V
= V
CC
- 0.2 V
= 5.5 V
= 2.2 V
= 3.0 V
= V
CC(DR)
- 0.2 V
=
=
=
=
=
=
=
=
4.5 V
-4.0 mA
4.5 V
8.0 mA
4.5 V
2.4 V
4.5 V
0.4 V
Min.
Max.
Unit
50
100
mA
µA
Supply Current - Standby Mode
(CMOS level)
Supply Current - Standby Mode
(TTL level)
Supply Current - Data Retention
Mode
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Input High Leakage Current
Input Low Leakage Current
Output Leakage Current
High at Three-State Outputs
Low at Three-State Outputs
I
CC(SB)
V
CC
V
E1
= V
E2
V
CC
V
E1
= V
E2
V
CC(DR)
V
E1
= V
E2
V
CC
I
OH
V
CC
I
OL
V
CC
V
OH
V
CC
V
OL
V
CC
V
IH
V
CC
V
IL
V
CC
V
OH
V
CC
V
OL
I
CC(SB)1
5
(typ. 2)
50
2.4
-
-
8.0
-
-2
-
0.4
-4.0
-
2
-
mA
µA
V
V
mA
mA
µA
µA
I
CC(DR)
V
OH
V
OL
I
OH
I
OL
I
IH
I
IL
= 5.5 V
= 5.5 V
= 5.5 V
=
0V
= 5.5 V
= 5.5 V
= 5.5 V
=
0V
I
OHZ
I
OLZ
-
-2
2
-
µA
µA
December 12, 1997
3
U62H64SA
Symbol
Switching Characteristics
Time to Output in Low-Z from
E1 LOW or E2 HIGH
G LOW
W HIGH
Cycle Time
Write Cycle Time
Read Cycle Time
Access Time
E1 LOW or E2 HIGH to Data Valid
G LOW to Data Valid
Address to Data Valid
Pulse Widths
Write Pulse Width
Chip Enable to End of Write
Setup Times
Address Setup Time
Chip Enable to End of Write
Write Pulse Width
Data Setup Time
Data Hold Time
Address Hold from End of Write
Output Hold Time from Address Change
E1 HIGH or E2 LOW to Output in High-Z
W LOW to Output in High-Z
G HIGH to Output in High-Z
E1 LOW or E2 HIGH to Power-Up
E1 HIGH or E2 LOW to Power-Down
Alt.
t
LZCE
t
LZOE
t
LZWE
t
WC
t
RC
t
ACE
t
OE
t
AA
t
WP
t
CW
t
AS
t
CW
t
WP
t
DS
t
DH
t
AH
t
OH
t
HZCE
t
HZWE
t
HZOE
t
PU
t
PD
IEC
t
en(E)
t
en(G)
t
en(W)
t
cW
t
cR
t
a(E)
t
a(G)
t
a(A)
t
w(W)
t
w(E)
t
su(A)
t
su(E)
t
su(W)
t
su(D)
t
h(D)
t
h(A)
t
v(A)
t
dis(E)
t
dis(W)
t
dis(G)
0
35
20
25
0
25
20
15
0
0
5
15
15
12
Min.
35
5
0
0
35
35
35
15
35
Max.
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Data Retention Mode E1-Controlled
V
CC
Data Retention Mode E2-Controlled
V
CC
V
CC(DR)
≥
2 V
t
rec
2.2 V
E1
0V
t
DR
0.8 V
Data Retention
t
rec
0.8 V
4.5 V
V
CC(DR)
≥
2 V
2.2 V
t
DR
0V
Data Retention
4.5 V
E2
V
E2(DR)
≥
V
CC(DR)
- 0.2 V or V
E2(DR)
≤
0.2 V
V
CC(DR)
- 0.2 V
≤
V
E1(DR)
≤
V
CC(DR)
+ 0.3 V
V
E1(DR)
≥
V
CC(DR)
- 0.2 V or V
E1(DR)
≤
0.2 V
V
E2(DR)
≤
0.2 V
Chip Deselect to Data Retention Time
Operating Recovery Time at V
CC(DR)
t
DR
: min 0 ns
t
rec
: min t
cR
4
December 12, 1997
U62H64SA
Test Configuration for Functional Check
5V
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
V
CC
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Input level according to the
relevant test measurement
V
IH
V
IL
ment of all 8 output pins
Simultaneous measure-
481
V
O
E1
E2
W
G
30 pF
1)
255
V
SS
1)
In measurement of t
dis(E)
, t
dis(W)
, t
dis(G)
, t
en(E)
, t
en(W)
, t
en(G)
the capacitance is 5 pF.
Capacitance
Input Capacitance
Output Capacitance
Conditions
V
CC
= 5.0 V
V
I
= V
SS
f
T
a
= 1 MHz
= 25
°C
Symbol
C
I
C
O
Min.
Max.
8
10
Unit
pF
pF
All pins not under test must be connected with ground by capacitors.
IC Code Number
Example
U62H64
Type
Package
S = SOP
S
A
35
Access Time
35 = 35 ns
Operating Temperature Range
A = -40 to 125 °C
The date of manufacture is given by the last 4 digits of the mark, the first 2 digits indicating the year, and the last
2 digits the calendar week.
December 12, 1997
5
MCU
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