Very Low Power CMOS SRAM
64K X 16 bit
Pb-Free and Green package materials are compliant to RoHS
BS616LV1010
FEATURES
Wide V
CC
operation voltage : 2.4V ~ 5.5V
Very low power consumption :
Operation current : 25mA (Max.) at 55ns
V
CC
= 3.0V
2mA (Max.) at 1MHz
O
Standby current : 0.5/1.5uA (Max.) at 70/85 C
Operation current : 45mA (Max.) at 55ns
V
CC
= 5.0V
5mA (Max.) at 1MHz
O
Standby current : 3/5uA (Max.) at 70/85 C
High speed access time :
-55
55ns(Max.) at V
CC
=2.7~5.5V
-70
70ns(Max.) at V
CC
=2.4~5.5V
Automatic power down when chip is deselected
Easy expansion with CE and OE options
I/O Configuration x8/x16 selectable by LB and UB pin.
Three state outputs and TTL compatible
Fully static operation
Data retention supply voltage as low as 1.5V
DESCRIPTION
The BS616LV1010 is a high performance, very low power CMOS
Static Random Access Memory organized as 65,536 by 16 bits and
operates form a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with maximum CMOS standby
current of 1.5/5uA at Vcc=3/5V at 85 C and maximum access time
of 55/70ns.
Easy memory expansion is provided by an active LOW chip enable
(CE) and active LOW output enable (OE) and three-state output
drivers.
The BS616LV1010 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BS616LV1010 is available in DICE form, JEDEC standard
44-pin TSOP II and 48-ball BGA package.
O
POWER CONSUMPTION
POWER DISSIPATION
PRODUCT
FAMILY
BS616LV1010DC
BS616LV1010AC
BS616LV1010EC
BS616LV1010AI
BS616LV1010EI
Industrial
O
-40 C to +85 C
O
OPERATING
TEMPERATURE
STANDBY
(I
CCSB1
, Max)
Operating
(I
CC
, Max)
PKG TYPE
V
CC
=3.0V
10MHz
f
Max.
V
CC
=5.0V
V
CC
=3.0V
1MHz
V
CC
=5.0V
10MHz
f
Max.
1MHz
Commercial
O
O
+0 C to +70 C
DICE
3.0uA
0.5uA
4mA
24mA
44mA
1.5mA
14mA
24mA
BGA-48-0608
TSOP II-44
5.0uA
1.5uA
5mA
25mA
45mA
2mA
15mA
25mA
BGA-48-0608
TSOP II-44
PIN CONFIGURATIONS
A4
A3
A2
A1
A0
CE
DQ0
DQ1
DQ2
DQ3
VCC
VSS
DQ4
DQ5
DQ6
DQ7
WE
A15
A14
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
DQ15
DQ14
DQ13
DQ12
VSS
VCC
DQ11
DQ10
DQ9
DQ8
NC
A8
A9
A10
A11
NC
BLOCK DIAGRAM
A8
A13
A15
A14
A12
A7
A6
A5
A4
2048
DQ0
.
.
.
.
.
.
DQ15
CE
WE
OE
UB
LB
V
CC
V
SS
16
.
.
.
.
.
.
16
Data
Output
Buffer
16
128
Column Decoder
7
Control
Address Input Buffer
Data
Input
Buffer
16
Column I/O
Write Driver
Sense Amp
Address
Input
Buffer
9
Row
Decoder
512 x 2048
512
Memory Array
BS616LV1010EC
BS616LV1010EI
1
A
B
C
D
E
F
G
H
LB
D8
D9
VSS
VCC
D14
D15
NC
2
OE
UB
D10
D11
D12
D13
NC
A8
3
A0
A3
A5
NC
NC
A14
A12
A9
4
A1
A4
A6
A7
NC
A15
A13
A10
5
A2
CE
D1
D3
D4
D5
WE
A11
6
NC
D0
D2
VCC
VSS
D6
D7
NC
A11 A9
A3
A2
A1
A0 A10
48-ball BGA top view
Brilliance Semiconductor, Inc.
reserves the right to change products and specifications without notice.
R0201-BS616LV1010
1
Revision
2.7
Oct.
2008
BS616LV1010
PIN DESCRIPTIONS
Name
A0-A15 Address Input
CE Chip Enable Input
Function
These 16 address inputs select one of the 65,536 x 16-bit in the RAM
CE is active LOW. Chip enable must be active when data read form or write to the
device. If chip enable is not active, the device is deselected and is in standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impendence state when OE is inactive.
LB and UB Data Byte Control Input
DQ0-DQ15 Data Input/Output
Ports
V
CC
V
SS
Lower byte and upper byte data input/output control pins.
There 16 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Ground
TRUTH TABLE
MODE
Chip De-selected
(Power Down)
CE
H
X
L
L
WE
X
X
H
H
OE
X
X
H
H
LB
X
H
L
X
L
UB
X
H
X
L
L
L
H
L
L
H
IO0~IO7
High Z
High Z
High Z
High Z
D
OUT
High Z
D
OUT
D
IN
X
D
IN
IO8~IO15
High Z
High Z
High Z
High Z
D
OUT
D
OUT
High Z
D
IN
D
IN
X
V
CC
CURRENT
I
CCSB
, I
CCSB1
I
CCSB
, I
CCSB1
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
Output Disabled
Read
L
H
L
H
L
L
Write
L
L
X
H
L
NOTES: H means V
IH
; L means V
IL
; X means don’t care (Must be V
IH
or V
IL
state)
R0201-BS616LV1010
2
Revision
2.7
Oct.
2008
BS616LV1010
ABSOLUTE MAXIMUM RATINGS
(1)
SYMBOL
V
TERM
T
BIAS
T
STG
P
T
I
OUT
OPERATING RANGE
UNITS
V
O
PARAMETER
Terminal Voltage with
Respect to GND
Temperature Under
Bias
Storage Temperature
Power Dissipation
DC Output Current
RATING
-0.5
(2)
RANG
Commercial
Industrial
AMBIENT
TEMPERATURE
0 C to + 70 C
-40 C to + 85 C
O
O
O
O
V
CC
2.4V ~ 5.5V
2.4V ~ 5.5V
to 7.0
-40 to +125
-60 to +150
1.0
20
C
C
O
W
mA
CAPACITANCE
(1)
(T
A
= 25
O
C, f = 1.0MHz)
SYMBOL PAMAMETER CONDITIONS MAX. UNITS
C
IN
C
IO
Input
Capacitance
Input/Output
Capacitance
V
IN
= 0V
V
I/O
= 0V
6
8
pF
pF
1. Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. –2.0V in case of AC pulse width less than 30 ns.
1. This parameter is guaranteed and not 100% tested.
DC ELECTRICAL CHARACTERISTICS (T
A
= -40
O
C to +85
O
C)
PARAMETER
NAME
V
CC
V
IL
V
IH
I
IL
I
LO
V
OL
V
OH
I
CC
(5)
I
CC1
I
CCSB
I
CCSB1
(6)
PARAMETER
Power Supply
Input Low Voltage
TEST CONDITIONS
MIN.
2.4
-0.5
(2)
TYP.
(1)
--
--
MAX.
5.5
0.8
(3)
UNITS
V
V
Input High Voltage
V
IN
= 0V to V
CC
CE= V
IH
V
I/O
= 0V to V
CC
,
CE= V
IH
or OE = V
IH
V
CC
= Max, I
OL
= 2.0mA
V
CC
= Min, I
OH
= -1.0mA
CE = V
IL
,
I
IO
= 0mA, f = F
MAX
CE = V
IL
,
I
IO
= 0mA, f = 1MHz
CE = V
IH
,
I
IO
= 0mA
CE≧V
CC
-0.2V
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
(4)
2.2
--
V
CC
+0.3
1
V
Input Leakage Current
--
--
uA
Output Leakage Current
--
--
1
uA
Output Low Voltage
--
--
0.4
V
Output High Voltage
Operating Power Supply
Current
Operating Power Supply
Current
Standby Current – TTL
2.4
V
CC
=3.0V
V
CC
=5.0V
V
CC
=3.0V
V
CC
=5.0V
V
CC
=3.0V
V
CC
=5.0V
V
CC
=3.0V
V
CC
=5.0V
--
--
25
45
2
5
0.5
1.0
1.5
5.0
V
--
--
mA
--
--
mA
--
--
0.02
0.4
mA
Standby Current – CMOS
O
--
uA
1. Typical characteristics are at T
A
=25 C and not 100% tested.
2. Undershoot: -1.0V in case of pulse width less than 20 ns.
3. Overshoot: V
CC
+1.0V in case of pulse width less than 20 ns.
4. F
MAX
=1/t
RC(MIN.).
O
5. I
CC (MAX.)
is 24mA/44mA at V
CC
=3.0V/5.0V and T
A
=70 C.
O
6. I
CCSB1(MAX.)
is 0.5uA/3.0uA at V
CC
=3.0V/5.0V and T
A
=70 C.
R0201-BS616LV1010
3
Revision
2.7
Oct.
2008
BS616LV1010
DATA RETENTION CHARACTERISTICS (T
A
= -40
O
C to +85
O
C)
SYMBOL
V
DR
I
CCDR
(3)
t
CDR
t
R
PARAMETER
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
O
TEST CONDITIONS
CE≧V
CC
-0.2V
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
CE≧V
CC
-0.2V
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
MIN.
1.5
TYP.
(1)
--
MAX.
--
UNITS
V
--
0.02
0.5
uA
0
See Retention Waveform
t
RC
(2)
--
--
ns
--
--
ns
1. V
CC
=1.5V, T
A
=25 C and not 100% tested.
2. t
RC
= Read Cycle Time.
O
3. I
CCDR(Max.)
is 0.3uA at T
A
=70 C.
LOW V
CC
DATA RETENTION WAVEFORM (CE Controlled)
Data Retention Mode
V
CC
V
CC
V
DR
≧1.5V
V
CC
t
CDR
V
IH
CE≧V
CC
- 0.2V
t
R
V
IH
CE
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing
Reference Level
Output Load
t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
WHZ
Others
Vcc / 0V
1V/ns
0.5Vcc
C
L
= 5pF+1TTL
C
L
= 30pF+1TTL
ALL INPUT PULSES
1 TTL
Output
C
(1)
L
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM “H” TO “L”
MAY CHANGE
FROM “L” TO “H”
DON’T CARE
ANY CHANGE
PERMITTED
DOES NOT
APPLY
OUTPUTS
MUST BE
STEADY
WILL BE CHANGE
FROM “H” TO “L”
WILL BE CHANGE
FROM “L” TO “H”
CHANGE :
STATE UNKNOW
CENTER LINE IS
HIGH INPEDANCE
“OFF” STATE
V
CC
GND
10%
90%
90%
10%
→ ←
Rise Time:
1V/ns
→ ←
Fall Time:
1V/ns
1. Including jig and scope capacitance.
R0201-BS616LV1010
4
Revision
2.7
Oct.
2008
BS616LV1010
AC ELECTRICAL CHARACTERISTICS (T
A
= -40
O
C to +85
O
C)
READ CYCLE
JEDEC
PARANETER
PARAMETER
NAME
NAME
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output Low Z
Chip Select to Output High Z
Data Byte Control to Output High Z
Output Enable to Output High Z
Data Hold from Address Change
(CE)
(LB, UB)
(CE)
(LB, UB)
(CE)
(LB, UB)
CYCLE TIME : 55ns
(V
CC
=2.7~5.5V)
MIN.
55
--
--
--
--
10
10
5
--
--
--
10
TYP.
--
--
--
--
--
--
--
--
--
--
--
--
MAX.
--
55
55
55
30
--
--
--
30
30
25
--
CYCLE TIME : 70ns
(V
CC
=2.4~5.5V)
MIN.
70
--
--
--
--
10
10
5
--
--
--
10
TYP.
--
--
--
--
--
--
--
--
--
--
--
--
MAX.
--
70
70
70
35
--
--
--
35
35
30
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UNITS
t
AVAX
t
AVQX
t
ELQV
t
BLQV
t
GLQV
t
ELQX
t
BLQX
t
GLQX
t
EHQZ
t
BHQZ
t
GHQZ
t
AVQX
t
RC
t
AA
t
ACS
t
BA
t
OE
t
CLZ
t
BE
t
OLZ
t
CHZ
t
BDO
t
OHZ
t
OH
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE 1
(1,2,4)
t
RC
ADDRESS
t
OH
D
OUT
t
AA
t
OH
R0201-BS616LV1010
5
Revision
2.7
Oct.
2008
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