EEWORLDEEWORLDEEWORLD

Part Number

Search

530KA115M000DG

Description
CMOS/TTL Output Clock Oscillator, 115MHz Nom, ROHS COMPLIANT, SMD, 6 PIN
CategoryPassive components    oscillator   
File Size215KB,12 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance  
Download Datasheet Parametric View All

530KA115M000DG Overview

CMOS/TTL Output Clock Oscillator, 115MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530KA115M000DG Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
package instructionROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Codeunknown
Other featuresTRAY
maximum descent time0.35 ns
Frequency Adjustment - MechanicalNO
frequency stability50%
JESD-609 codee4
Manufacturer's serial number530
Installation featuresSURFACE MOUNT
Nominal operating frequency115 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeCMOS/TTL
physical size7.0mm x 5.0mm x 1.85mm
longest rise time0.35 ns
Maximum supply voltage1.89 V
Minimum supply voltage1.71 V
Nominal supply voltage1.8 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Gold (Ni/Au)
Base Number Matches1
S i 5 3 0 / 5 31
R
EVISION
D
C
R Y S TA L
O
S C I L L A T O R
(XO)
(10 M H
Z T O
1.4 G H
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
NC
OE
GND
1
2
3
6
5
4
V
DD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
®
CLK–
CLK+
Si530 (LVDS/LVPECL/CML)
OE
NC
GND
1
2
3
6
5
4
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
CLK
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
OE
NC
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Rev. 1.1 6/07
Copyright © 2007 by Silicon Laboratories
Si530/531
STM320F103VC+w5100-->TCP
I have a STM320F103VC+W5100 module and want to communicate with PC through TCP/IP. I have referenced the examples and manuals, but there are a few things I don't understand. Please advise. 1. Is the c...
collean stm32/stm8
How does uversion know the memory usage of arm programs?
I use uversion4, lm3s8962 chip. I create a global variable uchar a[9000]100]; Logically, it should exceed the capacity of RAM, but how come there is no error after compiling? How can I know whether th...
heich_tech Microcontroller MCU
When printing on the STM32F103 serial port, the data transmission rate is limited
[size=6]Dear colleagues[/size], I have recently been working on a program that uses ADC to collect high-frequency signals (about 4K). I use a timer to trigger the ADC and transfer data through DMA for...
FireLife stm32/stm8
After simulating 18b20, everything is displayed. After adding 4 modules, it takes a while.
#include #include#include#define ucharunsigned char #define uintunsigned int staticucharth,tl,b,c,d,f,j,e;uint a, temp; sbit morehigh=P1^0 ; sbit high=P1^1 ; sbit low=P1^2 ; sbit morelow=P1^3 ; sbit R...
1322685712 MCU
Let's talk about the libraries in VHDL
I recently encountered the problem "Error (10327): VHDL error at and2.vhd(11): can't determine definition of operator ""+"" -- found 0 possible definitions" when programming in VHDL. I didn't know why...
wenhuawu FPGA/CPLD
Very basic textbook on digital circuits
Very basic textbook on digital circuits...
tarzanwl Analog electronics

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2877  2321  1743  1649  1840  58  47  36  34  38 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号