DATA SHEET
JANUARY 1999
LXT332
General Description
The LXT332 is a fully integrated Dual Line Interface Unit
(DLIU) for both 1.544 Mbps (T1) and 2.048 Mbps (E1)
applications. It features B8ZS/HDB3 encoders and
decoders, and a constant low output impedance transmitter
for high return loss. Transmit pulse shape is selectable for
various line lengths and cable types.
The LXT332 incorporates an advanced crystal-less digital
jitter attenuator, switchable to either the transmit or receive
side. This eliminates the need for an external quartz
crystal. It offers both a serial interface (SIO) for
microprocessor control and a hardware control mode for
stand-alone operation.
The LXT332 offers a variety of advanced diagnostic and
performance monitoring features. It uses an advanced
double-poly, double-metal CMOS process and requires
only a single 5-volt power supply.
Revision 2.1
Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation
Features
• Digital (crystal-less) jitter attenuation, selectable for
receive or transmit path, or may be disabled
• High transmit and receive return loss
• Constant low output impedance transmitter with
programmable equalizer shapes pulses to meet DSX-1
pulse template from 0 to 655 ft.
• Meets or exceeds industry specifications including
ITU G.703, ANSI T1.403, AT&T Pub 62411 and
ITU-T G.742
• Compatible with most industry standard framers
• Complete line driver, data recovery and clock
recovery functions
• Minimum receive signal of 500 mV, with selectable
slicer levels to improve SNR
• Local, remote, and dual loopback functions
• Built-In Self Test with QRSS Pattern Generator
• Transmit/Receive performance monitors with Driver
Fail Monitor (DFM) and Loss of Signal (LOS)
outputs
• Receiver jitter tolerance 0.4 UI from 40 kHz to 100 kHz
• Available in 44-pin PLCC and 44-pin QFP packages
Applications
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PCM/Voice Channel Banks
Data Channel Bank/Concentrator
T1/E1 multiplexer
Digital Access and Cross-connect Systems (DACS)
Computer to PBX interface (CPI & DMI)
SONET/SDH Multiplexers
Interfacing Customer Premises Equipment to a CSU
Digital Loop Carrier (DLC) terminals
LXT332 Block Diagram
QRSS / BPV Generator
TCLK
TPOS
TNEG
B8ZS/HDB3
Unipolar
Encoder
Encoder
Enable
Remote
Local
Loopback
Jitter
Attenuator
Transmit
Timing &
Control
TAOS
Enable
Equalizer
Monitor
DFM
Line
Driver
TTIP
TRING
DFM
LEN Select
Serial Word
Decoder
Enable RLOOP
Loopback
Enable
JASEL
LLOOP
Enable
Internal
Clock
Generator
MCLK
HFC
RTIP
RRING
INT0/1
PS0/1
CLKE
SCLK
SDI
SDO
RPOS
RNEG
RCLK
B8ZS/HDB3
Unipolar
Decoder
Peak
Detector
Timing &
Data
Recovery
QRSS Detector
LOS
Processor
Serial
Port
LOS
Transceiver 0
Transceiver 1
Refer to www.level1.com for most current information.
LXT332 Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation
OVERVIEW
In addition to the inherent advantages of a dual LIU, the
LXT332 also provides several advanced features that are
not available in other LXT300-series devices. All of the
added features are easily implemented. Many require only
a clock pulse to change from one mode to another. Some
features are available in Host mode only.
Additional Host-Mode
Features
High Frequency Clocks
The LXT332 provides a pair of high frequency clock
outputs, one for each LIU. These 8x clocks (12.352 MHz
for T1, 16.384 MHz for E1) are tied to the de-jittered clock
from the JA of the respective LIU.
Standard LXT332 Features
Tri-state Outputs
All LXT332 output pins can be forced to tri-state (high-Z).
Tri-state is controlled by the TRSTE pin.
Bipolar Violation Insertion
The same pins which provide the high frequency clocks can
also be used to insert bipolar violations into the outgoing
data stream. Violations can be inserted into each LIU port
independently.
Bipolar or Unipolar Data I/O
The LXT332 to framer interface can be either bipolar
(default) or unipolar (selectable). The unipolar I/O mode is
selected by applying MCLK to the TRSTE pin.
Built-In Self Test (QRSS)
The LXT332 can generate and transmit a Quasi Random
Signal Source (QRSS) pattern to Built-In Self Test (BIST)
applications. Logic errors and bipolar violations can be
inserted into the QRSS output. The LXT332 also detects
QRSS pattern synchronization and reports bit errors in the
received QRSS pattern data stream.
B8ZS or HDB3 Zero Suppression
The LXT332 incorporates zero suppression encoders and
decoders for use in the unipolar data I/O mode. The
encoders/decoders can be activated or deactivated by
changing the logic level on the re-mapped TNEG pin.
Selectable Jitter Attenuation
Jitter attenuation can be placed in either the transmit or
receive path or deactivated. The Jitter Attenuation Select
(JASEL) pin selects the jitter attenuation path. No crystal is
required.
AIS Detection
The LXT332 detects the AIS alarm signal on the receive
side independent of the loopback modes. When AIS is
detected (less than 3 zeros in 2048 bits), the LXT332
provides an indicator output.
Dual Loopback
Dual Loopback (DLOOP) enables simultaneous loopbacks
to both the framer and the line. The TCLK, TPOS and
TNEG framer inputs are routed through the jitter attenuator
and looped back to the RCLK, RPOS and RNEG outputs.
The RTIP/RRING line inputs are looped back through the
timing recovery block and line driver onto the TTIP/
TRING outputs.
2
LXT332 Pin Assignments and Signal Descriptions
PIN ASSIGNMENTS AND SIGNAL DESCRIPTIONS
Figures 1 and 2 identify the pins and signals for the PLCC
and QFP packages, respectively. Note that many pins have
two functions. The active function is determined by the
particular mode of operation selected. Table 1 describes the
Host mode signal functions, except signals that change
when in Unipolar Host mode. Table 2 describes signal
functions that change when in Unipolar Most mode.
Table 3 describes all Hardware mode signal functions,
except signals that change when in Unipolar mode. Table 4
describes signal functions that change when Unipolar
Hardware mode is selected.
Figure 1: LXT332 Pin Assignments (PLCC Package)
RPOS0 / RDATA0
6
RCLK0
TAOS0 / SCLK
LEN20 / VCQ0
LEN10 / INT1
LEN00 / INT0
MCLK
GND
TTIP0
TGND0
TVCC0
TRING0
5
4
3
2
1 44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
RCLK1
RLOOP1 / SDO
LEN21 / VCQE
LEN11 / SPE
LEN01 / VCQ1
JASEL
VCC
TTIP1
TGND1
TVCC1
TRING1
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28
LOS0 / PD0
LOS1 / PD1
RRING0
RRING1
LLOOP0 / CLKE
RLOOP0 / PS0
LLOOP1 / SDI
DFM
RTIP0
RTIP1
TAOS1 / PS1
LXT332PE
RPOS1 / RDATA1
TPOS0 / TDATA0
TPOS1 / TDATA1
RNEG0 / BPV0
RNEG1 / BPV1
TNEG0 / ECE0
TNEG1 / ECE1
TRSTE
TCLK0
TCLK1
3
LXT332 Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation
Figure 2: LXT332 Pin Assignments (QFP Package)
RPOS0 / RDATA0
44 43 42 41 40 39 38 37 36 35 34
RCLK0
TAOS0 / SCLK
LEN20 / VCQ0
LEN10 / INT1
LEN00 / INT0
MCLK
GND
TTIP0
TGND0
TVCC0
TRING0
RPOS1 / RDATA1
TPOS0 / TDATA0
TPOS1 / TDATA1
RNEG0 / BPV0
RNEG1 / BPV1
TNEG0 / ECE0
TNEG1 / ECE1
TRSTE
TCLK0
TCLK1
1
2
3
4
5
6
7
8
9
10
11
12 13 14 15 16 17 18 19 20 21 22
LLOOP0 / CLKE
RLOOP0 / PS0
LLOOP1 / SDI
DFM
RRING0
LOS0 / PD0
RRING1
LOS1 / PD1
RTIP0
RTIP1
TAOS1 / PS1
33
32
31
30
29
28
27
26
25
24
23
RCLK1
RLOOP1 / SDO
LEN21 / VCQE
LEN11 / SPE
LEN01 / VCQ1
JASEL
VCC
TTIP1
TGND1
TVCC1
TRING1
LXT332QE
4
LXT332 Pin Assignments and Signal Descriptions
Table 1: Host Mode and Bipolar Host Mode Pin Descriptions
Pin
QFP
39
Pin
PLCC
1
Symbol
TRSTE
I/O
1
DI
Description
Tristate Output Enable.
When held High, forces all output pins to high-Z (tri-
state).
When held Low, Bipolar I/O mode is selected. In this mode, the framer interface
is bipolar (TPOS/TNEG and RPOS/RNEG), and the B8ZS/HDB3 encoders are
disabled.
When clocked by MCLK, Unipolar I/O mode is selected. In this mode, the
framer interface is unipolar (TDATA and RDATA), and the TNEG and RNEG
pins are re-mapped. The TNEG pins are re-mapped as Encoder Enables (ECE) to
individually enable the B8ZS/HDB3 encoder/decoder for each port. The RNEG
pins are re-mapped as Bipolar Violation (BPV) indicators to report BPVs
detected at the respective ports.
40
41
42
43
44
2
3
4
5
6
TCLK0
TPOS0
(Bipolar)
TNEG0
(Bipolar)
RNEG0
(Bipolar)
RPOS0
(Bipolar)
DI
DI
DI
DO
DO
Transmit Clock - Port 0.
1.544 MHz for T1, 2.048 MHz for E1. The port 0
transmit data inputs are sampled on the falling edge of TCLK0.
Transmit Positive and Negative Data - Port 0.
In the Bipolar I/O mode, these
pins are the positive and negative sides of a bipolar input pair for
port 0. Data to be transmitted onto the twisted-pair line is input at these pins.
Receive Positive and Negative Data - Port 0.
In the Bipolar I/O mode, these
pins are the data outputs from port 0. A signal on RNEG corresponds to receipt
of a negative pulse on RTIP/RRING. A signal on RPOS corresponds to receipt
of a positive pulse on RTIP/RRING. RNEG/RPOS outputs are Non Return-to-
Zero (NRZ). The CLKE pin determines the clock edge at which these outputs
are stable and valid.
Receive Clock - Port 0.
Normally, this clock is recovered from the input signal.
Under Loss of Signal (LOS) conditions, RCLK0 is derived from MCLK.
Serial Clock.
SCLK shifts data into or out of the serial interface register of the
selected port.
1
2
7
8
RCLK0
SCLK
DO
DI
1. DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output; S = Power Supply.
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