V54C3256404VDLG7IPC datasheet, PDF

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V54C3256404VDLG7IPC: DescriptionSynchronous DRAM, 64MX4, 5.4ns, CMOS, PBGA54; Categorystorage storage; File Size720KB，56 Pages; ManufacturerProMOS Technologies Inc; Environmental Compliance

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V54C3256404VDLG7IPC Overview

Synchronous DRAM, 64MX4, 5.4ns, CMOS, PBGA54

V54C3256404VDLG7IPC Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
package instruction	FBGA, BGA54,9X9,32
Reach Compliance Code	compliant
Maximum access time	5.4 ns
Maximum clock frequency (fCLK)	143 MHz
I/O type	COMMON
interleaved burst length	1,2,4,8
JESD-30 code	S-PBGA-B54
memory density	268435456 bit
Memory IC Type	SYNCHRONOUS DRAM
memory width	4
Number of terminals	54
word count	67108864 words
character code	64000000
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	64MX4
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	FBGA
Encapsulate equivalent code	BGA54,9X9,32
Package shape	SQUARE
Package form	GRID ARRAY, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3 V
Certification status	Not Qualified
refresh cycle	8192
Continuous burst length	1,2,4,8,FP
Maximum standby current	0.001 A
Maximum slew rate	0.2 mA
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
Base Number Matches	1

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V54C3256(16/80/40)4VD*I

256Mbit SDRAM, INDUSTRIAL TEMPERATURE

3.3 VOLT, TSOP II / FBGA PACKAGE

16M X 16, 32M X 8, 64M X 4

System Frequency (f

)

Clock Cycle Time (t

CK3

)

Clock Access Time (t

AC3

) CAS Latency = 3

Clock Access Time (t

AC2

) CAS Latency = 2

166 MHz

6 ns

5.4 ns

7PC

143 MHz

7 ns

5.4 ns

143 MHz

7 ns

5.4 ns

6 ns

Features

■

4 banks x 4Mbit x 16 organization

4 banks x 8Mbit x 8 organization

4 banks x16Mbit x 4 organization

High speed data transfer rates up to 166 MHz

Full Synchronous Dynamic RAM, with all signals

referenced to clock rising edge

Single Pulsed RAS Interface

Data Mask for Read/Write Control

Four Banks controlled by BA0 & BA1

Programmable CAS Latency: 2, 3

Programmable Wrap Sequence: Sequential or

Interleave

Programmable Burst Length:

1, 2, 4, 8, and full page for Sequential Type

1, 2, 4, 8 for Interleave Type

Multiple Burst Read with Single Write Operation

Automatic and Controlled Precharge Command

Random Column Address every CLK (1-N Rule)

Power Down Mode

Auto Refresh and Self Refresh

Refresh Interval: 8192 cycles/64 ms

Available in 54 Pin TSOP II, 60 Ball FBGA, 54

Ball FBGA

LVTTL Interface

Single (3.0V~3.3 V)±0.3 V Power Supply

Industrial Temperature (TA): -40C to +85C

Description

The V54C3256(16/80/40)4VD*I is a four bank

Synchronous DRAM organized as 4 banks x 4Mbit

x 16, 4 banks x 8Mbit x 8, or 4 banks x 16Mbit x 4.

The V54C3256(16/80/40)4VD*I achieves high

speed data transfer rates up to 166 MHz by employ-

ing a chip architecture that prefetches multiple bits

and then synchronizes the output data to a system

clock

All of the control, address, data input and output

circuits are synchronized with the positive edge of

an externally supplied clock.

Operating the four memory banks in an inter-

leaved fashion allows random access operation to

occur at higher rate than is possible with standard

DRAMs. A sequential and gapless data rate of up to

166 MHz is possible depending on burst length,

CAS latency and speed grade of the device.

■

Device Usage Chart

Operating

Temperature

Range

-40°C to +85°C

Package Outline

T/S

•

Access Time (ns)

•

Power

•

7PC

•

Std.

•

Temperature

Mark

V54C3256(16/80/40)4VD*I Rev. 1.3 December 2007

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