IMISG502
April 1996
SYSTEM CLOCK CHIP
CMOS LSI
SPECTRUM SPREAD CLOCK
PRODUCT FEATURES
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Generates CPU Clock Signals for Microprocessor
Systems
Reduces Measured EMI by 10 db nominal
4V to 7V Operating Supply Range
Supports 80286-, 80386-, 80486-, Pentium™- and
29000-Based Designs
Wide Range of Selectable Output Frequencies
including 40, 33.3, 16.7
Single, Low Cost Crystal Used as Reference
Frequency
Glitch-Free Switching
50% Duty Cycle
Power Down Mode for Low Power Consumption
TTL or CMOS Compatible Outputs with 6 mA Drive
Capability
Low, Short and Long Term Jitter (cycle-to-cycle jitter
less than 50 ps)
16 PIN PDIP and 16 PIN SOIC (300 mil body)
package options
PRODUCT DESCRIPTION
The IMISG502 is a spectrum spread clock generator
specially designed for personal computers, laser
printers and other digital systems. IMISG502 uses a
patented concept to generate popular clock frequencies
that are intentionally broadbanded to reduce
electromagnetic
interference.
The
IMISG502
attenuates the radiated emission amplitudes from
products associated with either the clock harmonics or
any signals derived from the clock signals nominally 10
dB and could significantly reduce the cost of complying
with the regulatory requirements.
PRCLK is the broadbanded output and can be
programmed to generate 40, 33.3, 16.7 and 12 MHz
with S0 and S1 pins. A single, low cost external crystal
is required as reference frequency for the synthesizer.
Output modulation function can be turned off with the
SSON pin. Several power down modes add the
flexibility to operate the device in a completely static
mode to reduce standby currents and simplify system
board tests.
P-DIP/SOIC DIAGRAM
VDD
OSCin
OSCout
VSS
MPSEL
AVDD
S0
S1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
TEST
VDD
MPCLK
VSS
PRCLK
AVSS
LF1
SSON
BLOCK DIAGRAM
3
44.2
MHZ
2
REF
/4 or /12
14
MPCLK
MPSEL
LF
S0
S1
TEST
SSOR
5
10
7
8
16
9
APPLICATIONS
SPECTRUM
SPREAD
CLOCK
GEN
The IMISG502 eliminates the need for multiple
oscillators and generates the CPU clock signals for
personal computers, laser printers and other digital
systems. Supports 8086-, 80286-, 80386-, 80486-,
Pentium™- and 29000-based designs. IMISG502 can
be used with laptop or notebook computers to save
power by running the system slower than normal CPU
speeds or completely disabling the clocks in standby
mode.
/2
12
PRCLK
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571
Page
1
of 7
IMISG502
April 1996
SYSTEM CLOCK CHIP
CMOS LSI
SPECTRUM SPREAD CLOCK
PIN DESCRIPTION
OSCin OSCout-
These pins form an on-chip reference
oscillator when connected to terminals of an external
44.2 Mhz third overtone parallel resonant crystal. OSCin
may also serve as an input for an externally generated
CMOS level or AC coupled reference signal.
S0 and S1-
Standard frequency select inputs. These
inputs control the PRCLK frequency selection. S0-S1
inputs control the CPU clock frequencies. All these
inputs have internal pull-downs.
Table 1 shows
conditions.
the
output
frequency
selection
MPCLK -
This is a non modulated output. This output
can be programmed to be 3.7 Mhz or 11.06 Mhz. The
selection of these frequencies is controlled by the
MPSEL pin shown in Table 1.
PRCLK -
Output from the spectrum spread clock
generator. Frequency selection is shown on Table 1.
When the SSON pin is high, outputs are not modulated.
When SSON is low, sprectrum spread function is
enabled.
VSS-
Circuit ground.
VDD-
Positive power supply.
TEST-
Controls power down and Test Mode selection.
When high, S0-S1 and MPSEL controls the mode
selection as shown on Table 1 and Table 2. When low,
the device operates in normal mode. This pin has an
internal pull-down.
MPSEL
- Controls MPCLK output frequency selections.
Table 2 shows the selected frequencies for MPCLK.
This input has an internal pull-up.
SSON
- This is the control output for the clock
generator. It is a single-ended, tri-state output.
Component connections are shown in Figure 1.
LF1-
Loop filter, phase detector outputs for the clock
generators. It is a single-ended tristate output for use as
a loop error signal. See figure 1 for circuit.
PRCLK FREQUENCY SELECTION
INPUTS
OUTPUT
TEST
S1
S0
PRCLK
0
0
0
N/A
0
0
1
16.7 Mhz
0
1
0
33.3 Mhz
0
1
1
40.0 Mhz
1
0
0
0; Power Down
1
0
1
1; Power Down
1
1
0
TEST
1
1
1
Hi-Z
TABLE 1: When Power Down address is selected, the
VCO is turned off and the device goes into standby.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571
Page
2
AVDD-
Analog positive power supply.
AVSS-
Analog circuit ground.
Loop Filter
LF
2k
2200 pf
R2
C2
330 pf
C1
FIGURE 1
MPCLK FREQUENCY SELECTION
INPUTS
OUTPUT
TEST
MPSEL
S1
S0
MPCLK
0
0
X
X
3.7 Mhz
0
1
X
X
11.06 Mhz
1
X
0
0
0; Power Down
1
X
0
1
1; Power Down
1
X
1
0
TEST
1
X
1
1
Hi-Z
TABLE 2: When Power Down address is slected, the
VCO is turned off and the device goes to standy mode.
Phase detector is in tri-state mode.
of 7
IMISG502
April 1996
SYSTEM CLOCK CHIP
CMOS LSI
SPECTRUM SPREAD CLOCK
MAXIMUM RATINGS
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)< VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
Voltage Relative to VSS
Voltage Relative to VDD
Storage Temperature:
Ambient Temperature:
Maximum supply voltage:
-0.3
0.3V
-65° to +150°C
-0°C to + 70°C
7.0V
ELECTRICAL CHARACTERISTICS
Characteristic
Input Low Voltage
Input High Voltage
Symbol
VIL
VIH
Min
-
2.0
Typ
-
-
Max
0.8
-
Units
Vdc
Vdc
Input Low Current with Pull-up/ Pull-down
Output Low Voltage IOL = 6mA
Output High Voltage IOH=6mA
Tri-State Leakage Current
Static Supply Current
Dynamic Supply Current
Short Circuit Current
I
IH
/I
IL
VOL
VOH
IOZ
IDD
ICC
ISC
-
-
2.5
-
-
-
25
-
-
-
-
-
25
-
10/100
0.4
-
10
250
30
-
µA
Vdc
Vdc
µA
µA
mA
mA
VDD = 5V + 10%, TA = 0°C to +70°C
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571
Page
3
of 7
IMISG502
April 1996
SYSTEM CLOCK CHIP
CMOS LSI
SPECTRUM SPREAD CLOCK
SWITCHING CHARACTERISTICS
Characteristic
Output Rise and Fall Time Measured at 10% - 90%
of V
DD
Output Rise and Fall Time Measured at 0.8V - 2.0V
Output Duty Cycles
Jitter One Sigma
Symbol
tTLH,
tTHL
tTLH,
tTHL
TsymF1
Tj1s
Min
-
-
-
-
Typ
-
-
-
-
Max
5
3
45/55
2
Units
ns
ns
%
% of Fout
VDD = 5V + 10%, TA = 0°C to 70°C, CL = 15 pF
OSCILLATOR CHARACTERISTICS
Characteristic
Transconductance
Output Impedance
Input Capacitance
Output Capacitance
DC Bias Voltage
Start-up Time
Duty Cycle
Input Rise Time OSCIN
Symbol
g
m
Z
o
C
i
Co
V
B
t
s
TsymF1
ICLKr
Min
20
-
8
3
1.5
-
-
-
Typ
80
200
13
6
VDD/2
-
-
-
Max
180
800
18
9
3.5
2
45/55
20
Units
millimhos
ohms
pf
pf
Volt
ms
%
ns
@ VDD = 4.5V
Conditions
@ 44.2 MHz
@ 44.2 MHz
VCO CHARACTERISTICS
Characteristic
VCO Gain
Phase Detector Gain
Symbol
Ko
Kd
Min
35
100
Typ
55
145
Max
65
200
Units
MHz/volt
µA
Conditions
∆F/∆V
Measured with VCO Control at 2V - 3V
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571
Page
4
of 7
IMISG502
April 1996
SYSTEM CLOCK CHIP
CMOS LSI
SPECTRUM SPREAD CLOCK
EXTERNAL CONNECTIONS
VCC
DIGITAL GND PLANE
DVDD
C11
10uF
ANALOG GND PLANE
AVDD
R1
C10 10 Ohms
22uF
L1
1.5 uH
DVDD
C3
10pF
C5
C4
10pF
.033uF
L2 1.2uH
C6
.1uF
1
2
3
4
5
6
7
8
SG502
VDD
XIN
XOUT
VSS
MPSEL
AVDD
S0
S1
TEST
VDD
MPCLK
VSS
PRCLK
AVSS
LF1
SSON
16
15
14
13
12
11
10
9
C9
.1uF
DVDD
JP5
1
2
HEADER
C8
.1uF
AVDD
MPSEL JP1
S0 JP2
S1 JP3
TEST
JP4
DVDD
C2
2200pF
C1
330 pf
C7 10pF
NOTE1: KEEP C3, C4, C5, C6 CLOSE TO THEIR PINS (4,11,13,10,9 RESPECTIVELY)
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571
Page
5
of 7
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