May 2008
rev 0.4
3.3V 1:9 Clock Buffer
Features
•
•
•
One-Input to Nine-Output Buffer/Driver
Buffers all frequencies from DC to 133.33MHz
Low power consumption for mobile applications
Less than 32mA at 66.6MHz with unloaded
outputs
•
•
•
•
•
Input-Output delay: 6nS(max)
Output-output skew less than 250pS
16 pin SOIC Package
Supply Voltage:3.3V±0.3V
Commercial and Industrial temperature range
PCS2P2309NZ
Functional Description
PCS2P2309NZ is a low-cost high-speed buffer designed to
accept one clock input and distribute up to nine clocks in
mobile PC systems and desktop PC systems. The device
operates at 3.3V and outputs can run up to 133.33MHz.
PCS2P2309NZ is designed for low EMI and power
optimization and consumes less than 32mA at 66.6MHz,
making it ideal for the low-power requirements of mobile
systems. It is available in an 16 pin SOIC Package over
Commercial and Industrial temperature range.
Block Diagram
BUF_IN
OUTPUT1
OUTPUT2
OUTPUT3
OUTPUT4
OUTPUT5
OUTPUT6
OUTPUT7
OUTPUT8
OUTPUT9
PulseCore Semiconductor
1715,S.Bascom Avenue,Suite200,Campbell,CA 95008• Tel: 408-879-9077
•
Fax: 408-8879-9018
•
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
May 2008
rev 0.4
Pin Configuration
PCS2P2309NZ
BUF_IN
OUTPUT1
OUTPUT2
V
DD
GND
1
2
3
4
5
PCS2P2309NZ
16
15
14
13
12
11
10
9
OUTPUT9
OUTPUT8
OUTPUT7
V
DD
GND
OUTPUT6
OUTPUT5
GND
OUTPUT3 6
OUTPUT4
V
DD
7
8
Pin Description
Pin#
4, 8, 13
5, 9, 12
1
2, 3, 6, 7, 10, 11, 14, 15, 16
Pin Name
V
DD
GND
BUF_IN
OUTPUT [1:9]
Description
3.3V Digital Voltage Supply
Ground
Input Clock
Outputs
Absolute Maximum Ratings
Parameter
Supply Voltage to Ground Potential
DC Input Voltage (Except REF)
DC Input Voltage (REF)
Storage Temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage
(As per JEDEC STD22- A114-B)
Min
-0.5
-0.5
-0.5
-65
Max
+4.6
V
DD
+ 0.5
7
+150
260
150
2000
Unit
V
V
V
°C
°C
°C
V
Note: These are stress ratings only and functional usage is not implied. Exposure to absolute maximum ratings for prolonged periods can
affect device reliability.
3.3V 1:9 Clock Buffer
Notice: The information in this document is subject to change without notice.
2 of 8
May 2008
rev 0.4
Operating Conditions
Parameter
V
DD
T
A
C
L
C
IN
BUF_IN,
OUTPUT
[1:9]
t
PU
Supply Voltage
Commercial Temp.
Industrial Temp.
Load Capacitance, Fout < 100MHz
Load Capacitance,100MHz < Fout < 133.33MHz
Input Capacitance
Operating Frequency
Power-up time for all V
DD
's to reach minimum specified voltage (power
ramps must be monotonic)
PCS2P2309NZ
Description
Min
3.0
0
-40
Max
3.6
70
85
30
15
7
Unit
V
°C
°C
pF
pF
pF
MHz
mS
DC
0.05
133.33
50
Electrical Characteristics for Commercial and Industrial Temperature Devices
Symbol
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
Parameter
Input LOW Voltage
1
Input HIGH Voltage
1
Input LOW Current
Input HIGH Current
Output LOW Voltage
2
Output HIGH Voltage
2
Supply
Current
Commercial temp.
Industrial temp.
Test Conditions
Min
2.2
Max
0.8
Unit
V
V
µA
µA
V
V
V
IN
= 0V
V
IN
= V
DD
I
OL
= 12 mA
I
OH
= -12 mA
Unloaded outputs at 66.66MHz
2.4
50.0
100.0
0.4
30
32
mA
Switching Characteristics for Commercial and Industrial Temperature Devices
3
Symbol
t
3
t
4
t
D
Parameter
Rise Time
2
Fall Time
2
Duty Cycle
2
= t
2
÷t
1
Test Conditions
Measured between 0.8V and 2.0V
Measured between 2.0V and 0.8V
Measured at 1.4V (For an Input
Clock Duty Cycle 50%)
All outputs equally loaded
Min
Typ
1.5
1.5
Max
2
2
55
Unit
nS
nS
%
45
50
t
5
Output to Output Skew
2
±250
pS
t
6
Propagation Delay,
BUF_IN Rising Edge to
2
OUTPUT Rising Edge
Measured at V
DD
/2
4
6
nS
Note:
1. BUF_IN input has a threshold voltage of V
DD
/2.
2. Parameter is guaranteed by design and characterization. It is not 100% tested in production.
3. All parameters specified with loaded outputs.
3.3V 1:9 Clock Buffer
Notice: The information in this document is subject to change without notice.
3 of 8
May 2008
rev 0.4
Switching Waveforms
Duty Cycle Timing
t
1
t
2
PCS2P2309NZ
1.4V
OUTPUT
1.4V
1.4V
All Outputs Rise/Fall Time
2V
0.8V
2V
0.8V
VDD
OUTPUT
t
3
t
4
0V
Output-Output Skew
1.4V
OUTPUT
1.4V
OUTPUT
t5
Input-Output Propagation Delay
V
DD
/2
INPUT
V
DD
/2
OUTPUT
3.3V 1:9 Clock Buffer
Notice: The information in this document is subject to change without notice.
4 of 8
May 2008
rev 0.4
Test Circuit
PCS2P2309NZ
BUF-IN
V
DD
+3.3V
3
0.1uF
PCS2P2309NZ
GND
3
OUTPUT
CL
3.3V 1:9 Clock Buffer
Notice: The information in this document is subject to change without notice.
5 of 8
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