Intel
®
Pentium
®
III Processor for the
SC242 at 450 MHz to 1.0 GHz
Datasheet
Product Features
s
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Available in 1.0B GHz, 933, 866, 800EB,
733, 667, 600B, 600EB, 533B, and 533EB
MHz speeds support a 133 MHz system
bus (‘B’ denotes support for a 133 MHz
system bus where a processor is available
at the same specific core frequency in
seperate 100 MHz and 133 MHz Front Side
Bus versions; ‘E’ denotes support for
Advanced Transfer Cache and Advanced
System Buffering)
Available in 1.0 GHz, 850, 800, 750, 700,
650, 600E, 600, 550E, 550, 500, and
450 MHz speeds support a 100 MHz
system bus (‘E’ denotes support for
Advanced Transfer Cache and Advanced
System Buffering)
Available in versions that incorporate
256-KB Advanced Transfer Cache (on-die,
full speed Level 2 (L2) cache with Error
Correcting Code (ECC)) or versions that
incorporate a discrete, half-speed, 512-KB
in-package L2 cache with ECC
Dual Independent Bus (DIB) architecture
increases bandwidth and performance over
single-bus processors
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Internet Streaming SIMD Extensions for
enhanced video, sound and 3D
performance
Binary compatible with applications
running on previous members of the Intel
microprocessor line
Dynamic execution micro architecture
Power Management capabilities
— System Management mode
— Multiple low-power states
Intel Processor Serial Number
Optimized for 32-bit applications running
on advanced 32-bit operating systems
Single Edge Contact Cartridge (S.E.C.C.)
and S.E.C.C.2 packaging technology; the
S.E.C. cartridges deliver high performance
with improved handling protection and
socketability
Integrated high performance 16 KB
instruction and 16-KB data, nonblocking,
level one cache
Enables systems which are scaleable up to
two processors
Error-correcting code for System Bus data
The Intel
®
Pentium
®
III
processor is designed for high-performance desktops and for
workstations and servers. It is binary compatible with previous Intel Architecture processors.
The Pentium
III
processor provides great performance for applications running on advanced
operating systems such as Microsoft Windows* 98, Windows NT* and UNIX*. This is achieved
by integrating the best attributes of Intel processors—the dynamic execution, Dual Independent
Bus architecture plus Intel
®
MMX™ technology and Internet Streaming SIMD Extensions—
bringing a new level of performance for systems buyers. ThePentium
III
processor is scaleable to
two processors in a multiprocessor system and extends the power of the Intel
®
Pentium
®
II
processor with performance headroom for business media, communication and internet
capabilities. Systems based on Pentium
III
processors also include the latest features to simplify
system management and lower the cost of ownership for large and small business environments.
The Pentium
III
processor offers great performance for today’s and tomorrow’s applications.
SC242 / SECC2 Package
Document Number:
244452-009
July 2002
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL
®
PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined”. Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Pentium
®
III processor may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Intel, Pentium, Celeron, MMX, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States
and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2002, Intel Corporation
Datasheet
Contents
1.0
Introduction......................................................................................................................... 9
1.1
Terminology.........................................................................................................10
1.1.1 S.E.C.C.2 and S.E.C.C. Packaged Processor Terminology ..................10
1.1.2 Processor Naming Convention...............................................................11
Related Documents.............................................................................................12
Processor System Bus and V
REF
........................................................................13
Clock Control and Low Power States..................................................................14
2.2.1 Normal State—State 1 ...........................................................................15
2.2.2 AutoHALT Powerdown State—State 2...................................................15
2.2.3 Stop-Grant State—State 3 .....................................................................15
2.2.4 HALT/Grant Snoop State—State 4 ........................................................16
2.2.5 Sleep State—State 5..............................................................................16
2.2.6 Deep Sleep State—State 6 ....................................................................16
2.2.7 Clock Control..........................................................................................17
Power and Ground Pins ......................................................................................17
Decoupling Guidelines ........................................................................................17
2.4.1 Processor VCC
CORE
Decoupling............................................................18
2.4.2 Processor System Bus AGTL+ Decoupling............................................18
Processor System Bus Clock and Processor Clocking .......................................18
Voltage Identification ...........................................................................................18
Processor System Bus Unused Pins...................................................................20
Processor System Bus Signal Groups ................................................................20
2.8.1 Asynchronous vs. Synchronous for System Bus Signals .......................21
2.8.2 System Bus Frequency Select Signal (BSEL0)......................................22
Test Access Port (TAP) Connection....................................................................23
Maximum Ratings................................................................................................24
Processor DC Specifications...............................................................................25
AGTL+ System Bus Specifications .....................................................................32
System Bus AC Specifications ............................................................................32
BCLK, PICCLK, and PWRGOOD Signal Quality Specifications and
Measurement Guidelines ....................................................................................40
AGTL+ and Non-AGTL+ Overshoot/Undershoot Specifications and
Measurement Guidelines ....................................................................................41
3.2.1 Overshoot/Undershoot Magnitude .........................................................41
3.2.2 Overshoot/Undershoot Pulse Duration...................................................42
3.2.3 Overshoot/Undershoot Activity Factor....................................................42
3.2.4 Reading Overshoot/Undershoot Specification Tables............................43
3.2.5 Determining If a System Meets the Overshoot/Undershoot
Specifications .........................................................................................44
AGTL+ and Non-AGTL+ Ringback Specifications and Measurement
Guidelines ...........................................................................................................46
3.3.1 Settling Limit Guideline...........................................................................48
1.2
2.0
2.1
2.2
Electrical Specifications....................................................................................................13
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
3.0
3.1
3.2
Signal Quality Specifications ............................................................................................40
3.3
Datasheet
3
4.0
Thermal Specifications and Design Considerations......................................................... 49
4.1
Thermal Specifications........................................................................................ 50
4.1.1 Thermal Diode........................................................................................ 53
S.E.C.C. Mechanical Specifications.................................................................... 54
S.E.C.C.2 Mechanical Specification.................................................................... 61
S.E.C.C.2 Structural Mechanical Specification ................................................... 67
Processor Package Materials Information .......................................................... 69
Intel
®
Pentium
®
III Processor Signal Listing........................................................ 69
Intel
®
Pentium
®
III Processor Core Pad to Substrate Via Assignments .............. 76
5.6.1 Processor Core Pad Via Assignments (CPUID=067xh)......................... 76
5.6.2 Processor Core Signal Assignments (CPUID=067xh) ........................... 76
5.6.3 Processor Core Pad Via Assignments (CPUID=068xh)......................... 87
Introduction ......................................................................................................... 88
Fan Heatsink Mechanical Specifications............................................................. 88
6.2.1 Intel
®
Boxed Processor Fan Heatsink Dimensions ................................ 88
6.2.2 Intel
®
Boxed Processor Fan Heatsink Weight........................................ 90
6.2.3 Intel
®
Boxed Processor Retention Mechanism....................................... 90
Fan Heatsink Electrical Requirements ................................................................ 91
6.3.1 Fan Heatsink Power Supply ................................................................... 91
Fan Heatsink Thermal Specifications.................................................................. 92
6.4.1 Intel
®
Boxed Processor Cooling Requirements...................................... 92
Alphabetical Signals Reference .......................................................................... 93
Signal Summaries ............................................................................................. 100
5.0
S.E.C.C. and S.E.C.C.2 Mechanical Specifications......................................................... 54
5.1
5.2
5.3
5.4
5.5
5.6
6.0
Boxed Processor Specifications....................................................................................... 88
6.1
6.2
6.3
6.4
7.0
Intel
®
Pentium
®
III Processor Signal Description ............................................................. 93
7.1
7.2
4
Datasheet
Figures
1
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3
4
5
6
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8
9
10
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Second Level (L2) Cache Implementation ........................................................... 9
AGTL+ Bus Topology ..........................................................................................14
Stop Clock State Machine ...................................................................................14
BSEL[1:0] Example for a 100 MHz System Design (100 MHz Processor
Installed)..............................................................................................................22
BSEL[1:0] Example for a 100/133 MHz Capable System
(100 MHz Processor Installed) ............................................................................23
BSEL[1:0] Example for a 100/133 MHz Capable System
(133 MHz Processor Installed) ............................................................................23
BCLK, PICCLK, and TCK Generic Clock Waveform...........................................37
System Bus Valid Delay Timings ........................................................................38
System Bus Setup and Hold Timings..................................................................38
System Bus Reset and Configuration Timings....................................................38
Power-On Reset and Configuration Timings.......................................................39
Test Timings (TAP Connection) ..........................................................................39
Test Reset Timings .............................................................................................39
BCLK and PICCLK Generic Clock Waveform .....................................................40
Maximum Acceptable AGTL+ and Non-AGTL+ Overshoot/Undershoot
Waveform ............................................................................................................46
Low to High AGTL+ and Non-AGTL+ Receiver Ringback Tolerance .................48
Signal Overshoot/Undershoot, Settling Limit, and Ringback...............................48
S.E.C.Cartridge — 3-Dimensional View..............................................................49
S.E.C.Cartridge 2 — Substrate View ..................................................................50
Processor Functional Die Layout (CPUID=0686h)..............................................52
Processor Functional Die Layout (up to CPUID=0683h).....................................52
S.E.C.C. Packaged Processor — Multiple Views................................................54
S.E.C.C. Packaged Processor — Extended Thermal Plate Side
Dimensions..........................................................................................................55
S.E.C.C. Packaged Processor — Bottom View Dimensions...............................55
S.E.C.C. Packaged Processor — Latch Arm, Extended Thermal Plate Lug,
and Cover Lug Dimensions .................................................................................56
S.E.C.C. Packaged Processor — Latch Arm, Extended Thermal Plate,
and Cover Detail Dimensions (Reference Dimensions Only)..............................57
S.E.C.C. Packaged Processor — Extended Thermal Plate Attachment
Detail Dimensions ...............................................................................................58
S.E.C.C. Packaged Processor Substrate — Edge Finger Contact
Dimensions..........................................................................................................59
S.E.C.C. Packaged Processor — Extended Thermal Plate Attachment
Detail Dimensions, Continued .............................................................................59
S.E.C.C. Packaged Processor Substrate — Edge Finger Contact
Dimensions, Detail A ...........................................................................................60
Intel
®
Pentium® III Processor Markings (S.E.C.C. Packaged Processor)...........60
S.E.C.C.2 Packaged Processor — Multiple Views..............................................61
S.E.C.C.2 Packaged Processor Assembly — Primary View...............................62
S.E.C.C.2 Packaged Processor Assembly — Cover View with Dimensions ......62
S.E.C.C.2 Packaged Processor Assembly — Heatsink Attach Boss Section.....63
S.E.C.C.2 Packaged Processor Assembly — Side View ....................................63
Detail View of Cover in the Vicinity of the Substrate Attach Features.................63
S.E.C.C.2 Packaged Processor Substrate — Edge Finger Contact
Dimensions..........................................................................................................64
Datasheet
5
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