DATASHEET
X1205
2-Wire™ RTC Real Time Clock/Calendar
FEATURES
• Real Time Clock/Calendar
—Tracks time in Hours, Minutes, and Seconds
—Day of the Week, Day, Month, and Year
• 2 Polled Alarms (Non-volatile)
—Settable on the Second, Minute, Hour, Day of
the Week, Day, or Month
—Repeat Mode (periodic interrupts)
• Oscillator Compensation on Chip
—Internal Feedback Resistor and Compensation
Capacitors
—64 Position Digitally Controlled Trim Capacitor
—6 Digital Frequency Adjustment Settings to
±30ppm
• Battery Switch or Super Cap Input
• 2-Wire™ Interface Interoperable with I
2
C*
—400kHz Data Transfer Rate
• Low Power CMOS
—1.25µA Operating Current (Typical)
• Small Package Options
—8 Ld SOIC and 8 Ld TSSOP
• Repetitive Alarms
• Temperature Compensation
• Pb-Free Plus Anneal Available (RoHS Compliant)
APPLICATIONS
• Utility Meters
• HVAC Equipment
• Audio/Video Components
BLOCK DIAGRAM
OSC
Compensation
32.768kHz
X1
X2
Oscillator
Frequency
Divider
1Hz
Timer
Calendar
Logic
Time
Keeping
Registers
(SRAM)
FN8097
Rev 3.00
May 2, 2006
•
•
•
•
•
•
•
•
•
•
•
•
Set Top Box/Television
Modems
Network Routers, Hubs, Switches, Bridges
Cellular Infrastructure Equipment
Fixed Broadband Wireless Equipment
Pagers/PDA
POS Equipment
Test Meters/Fixtures
Office Automation (Copiers, Fax)
Home Appliances
Computer Products
Other Industrial/Medical/Automotive
DESCRIPTION
The X1205 device is a Real Time Clock with
clock/calendar, two polled alarms, oscillator
compensation, and battery backup switch.
The oscillator uses an external, low-cost 32.768kHz
crystal. All compensation and trim components are
integrated on the chip. This eliminates several external
discrete components and a trim capacitor, saving
board area and component cost.
The Real-Time Clock keeps track of time with
separate registers for Hours, Minutes, and Seconds.
The Calendar has separate registers for Date, Month,
Year and Day-of-week. The calendar is correct
through 2099, with automatic leap year correction.
Mask
8
Interrupt Enable
Alarm
SCL
SDA
Serial
Interface
Decoder
Control
Decode
Logic
Control
Registers
(EEPROM)
Status
Registers
(SRAM)
Alarm
Compare
Alarm Regs
(EEPROM)
IRQ
FN8097 Rev 3.00
May 2, 2006
Page 1 of 22
X1205
PIN DESCRIPTIONS
X1205
8 Ld SOIC
X1
X2
IRQ
V
SS
1
2
3
4
8
7
6
5
V
CC
V
BACK
SCL
SDA
V
BACK
V
CC
X1
X2
8 Ld TSSOP
1
2
3
4
8
7
6
5
SCL
SDA
V
SS
IRQ
NC = No internal connection
Ordering Information
PART NUMBER
X1205S8*
X1205S8Z* (Note)
X1205S8I*
X1205S8IZ* (Note)
X1205V8*
X1205V8Z* (Note)
X1205V8I*
X1205V8IZ* (Note)
PART MARKING
X1205
X1205 Z
X1205 I
X1205 Z I
1205
1205 Z
1205I
1205I Z
V
CC
RANGE (V)
2.7 to 5.5
TEMP RANGE (°C)
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
PACKAGE
8 Ld SOIC (150 mil)
8 Ld SOIC (150 mil) (Pb Free)
8 Ld SOIC (150 mil)
8 Ld SOIC (150 mil) (Pb Free)
8 Ld TSSOP (4.4mm)
8 Ld TSSOP (4.4mm) (Pb-free)
8 Ld TSSOP (4.4mm)
8 Ld TSSOP (4.4mm) (Pb-free)
PKG. DWG. #
MDP0027
MDP0027
MDP0027
MDP0027
M8.173
M8.173
M8.173
M8.173
*Add “T1” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
PIN ASSIGNMENTS
Pin Number
SOIC
1
2
3
4
5
TSSOP
3
4
5
6
7
Symbol
X1
X2
IRQ
V
SS
SDA
Brief Description
X1.
The X1 pin is the input of an inverting amplifier and should be connected to one pin
of a 32.768kHz quartz crystal.
X2.
The X2 pin is the output of an inverting amplifier and should be connected to one pin
of a 32.768kHz quartz crystal.
Interrupt Output – IRQ.
This is an interrupt signal output. This signal notifies a host proces-
sor that an alarm has occurred and requests action. It is an open drain active low output.
V
SS
.
Serial Data (SDA).
SDA is a bidirectional pin used to transfer data into and out of the
device. It has an open drain output and may be wire ORed with other open drain or open
collector outputs.
Serial Clock (SCL).
The SCL input is used to clock all data into and out of the device.
V
BACK
.
This input provides a backup supply voltage to the device. V
BACK
supplies power
to the device in the event the V
CC
supply fails. This pin can be connected to a battery, a
Supercap or tied to ground if not used.
V
CC
.
6
7
8
1
SCL
V
BACK
V
CC
8
2
FN8097 Rev 3.00
May 2, 2006
Page 2 of 22
X1205
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ................... -65°C to +135°C
Storage Temperature ........................ -65°C to +150°C
Voltage on V
CC
, V
BACK
and IRQ
pin (respect to ground) ............................-0.5V to 7.0V
Voltage on SCL, SDA, X1 and X2
pin (respect to ground) ............... -0.5V to 7.0V or 0.5V
above V
CC
or V
BACK
(whichever is higher)
DC Output Current .............................................. 5 mA
Lead Temperature (Soldering, 10 sec) .............. 300°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation
of the device at these or any other conditions above
those indicated in the operational sections of this specifi-
cation is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect device
reliability.
DC OPERATING CHARACTERISTICS
(Temperature = -40°C to +85°C, unless otherwise stated.)
Symbol
V
CC
V
BACK
V
CB
V
BC
Parameter
Main Power Supply
Backup Power Supply
Switch to Backup Supply
Switch to Main Supply
Conditions
Min
2.7
1.8
V
BACK
-0.2
V
BACK
Typ
Max
5.5
5.5
V
BACK
-0.1
V
BACK
+0.2
Unit
V
V
V
V
Notes
OPERATING CHARACTERISTICS
Symbol
I
CC1
I
CC2
I
CC3
I
BACK
I
LI
I
LO
V
IL
V
IH
V
HYS
V
OL
Parameter
Read Active Supply
Current
Program Supply Current
(nonvolatile)
Main Timekeeping
Current
Timekeeping Current
Conditions
V
CC
= 2.7V
V
CC
= 5.0V
V
CC
= 2.7V
V
CC
= 5.0V
V
CC
= 2.7V
V
CC
= 5.0V
V
BACK
= 1.8V
V
BACK
= 3.3V
Min
Typ
Max
400
800
2.5
3.0
10
20
Unit
µA
µA
mA
mA
µA
µA
µA
µA
Notes
1, 5, 7, 14
2, 5, 7, 14
3, 7, 8, 14, 15
3, 6, 9, 14, 15
“See Perfor-
mance Data”
1.25
1.5
10
10
-0.5
V
CC
x 0.7 or
V
BACK
x 0.7
V
CC
x 0.2 or
V
BACK
x 0.2
V
CC
+ 0.5 or
V
BACK
+ 0.5
Input Leakage Current
Output Leakage Current
Input LOW Voltage
Input HIGH Voltage
Schmitt Trigger Input
Hysteresis
Output LOW Voltage for
SDA/IRQ
V
CC
related level
V
CC
= 2.7V
V
CC
= 5.5V
µA
µA
V
V
V
10
10
13
13
13
11
.05 x V
CC
or
.05 x V
BACK
0.4
0.4
V
FN8097 Rev 3.00
May 2, 2006
Page 3 of 22
X1205
Notes: (1) The device enters the Active state after any start, and remains active: for 9 clock cycles if the Device Select Bits in the Slave Address
Byte are incorrect or until 200nS after a stop ending a read or write operation.
(2) The device enters the Program state 200nS after a stop ending a write operation and continues for t
WC
.
(3) The device goes into the Timekeeping state 200nS after any stop, except those that initiate a nonvolatile write cycle; t
WC
after a stop
that initiates a nonvolatile write cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave
Address Byte.
(4) For reference only and not tested.
(5) V
IL
= V
CC
x 0.1, V
IH
= V
CC
x 0.9, f
SCL
= 400KHz
(6) V
CC
= 0V
(7) V
BACK
= 0V
(8) V
SDA
= V
SCL
=V
CC
, Others = GND or V
CC
(9) V
SDA
=V
SCL
=V
BACK
, Others = GND or V
BACK
(10)V
SDA
= GND or V
CC
, V
SCL
= GND or V
CC
(11)I
OL
= 3.0mA at 5V, 1mA at 2.7V
(13)Threshold voltages based on the higher of Vcc or Vback.
(14)Using recommended crystal and oscillator network applied to X1 and X2 (25°C).
(15)Typical values are for T
A
= 25°C
Capacitance
T
A
= 25°C, f = 1.0 MHz, V
CC
= 5V
Symbol
C
OUT(1)
C
IN(1)
Parameter
Output Capacitance (SDA, IRQ)
Input Capacitance (SCL)
Max.
10
10
Units
pF
pF
Test Conditions
V
OUT
= 0V
V
IN
= 0V
Notes: (1) This parameter is not 100% tested.
(2) The input capacitance between x1 and x2 pins can be varied between 5pF and 19.75pF by using analog trimming registers
AC CHARACTERISTICS
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing
Levels
Output Load
V
CC
x 0.1 to V
CC
x 0.9
10ns
V
CC
x 0.5
Standard Output Load
Figure 1. Standard Output Load for testing the device with V
CC
= 5.0V
Equivalent AC Output Load Circuit for V
CC
= 5V
5.0V
For V
OL
= 0.4V
and I
OL
= 3 mA
IRQ
100pF
806
100pF
5.0V
1533
SDA
1316
FN8097 Rev 3.00
May 2, 2006
Page 4 of 22
X1205
AC Specifications
(T
A
= -40°C to +85°C, VCC = +2.7V to +5.5V, unless otherwise specified.)
Symbol
f
SCL
t
IN
t
AA
t
BUF
t
LOW
t
HIGH
t
SU:STA
t
HD:STA
t
SU:DAT
t
HD:DAT
t
SU:STO
t
DH
t
R
t
F
Cb
SCL Clock Frequency
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus must be free before a new transmission can start
Clock LOW Time
Clock HIGH Time
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
Data In Hold Time
Stop Condition Setup Time
Data Output Hold Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Capacitive load for each bus line
1.3
1.3
0.6
0.6
0.6
100
0
0.6
50
20 +.1Cb
(1)(2)
20 +.1Cb
(1)(2)
300
300
400
50
(1)
0.9
Parameter
Min.
Max.
400
Units
kHz
ns
s
s
s
s
s
s
ns
s
s
ns
ns
ns
pF
Notes: (1) This parameter is not 100% tested.
(2) Cb = total capacitance of one bus line in pF.
TIMING DIAGRAMS
Bus Timing
t
F
SCL
t
SU:STA
SDA IN
t
HD:STA
t
SU:DAT
t
HD:DAT
t
SU:STO
t
HIGH
t
LOW
t
R
t
AA
SDA OUT
t
DH
t
BUF
FN8097 Rev 3.00
May 2, 2006
Page 5 of 22
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