External Memory Solution for Lucent’s LUCTAPC640 ATM Port Controller
FEATURES
s
Clock speeds:
• SDRAM: 100 MHz
s
100% tested to timing requirements of LUCTAPC640’s memory
interface
s
Packaging:
• 153 pin BGA, 14mm x 22mm
s
3.3V Operating supply voltage
s
Direct control interface to both the BRAM and PRAM ports on
the LUCTAPC640
s
62% space savings vs. monolithic solution
s
Reduced system inductance and capacitance
DESCRIPTION
The WED9LAPC2B16P8BC is a 3.3V, 4M x 32 Synchronous
DRAM and a 2M x 8 Synchronous DRAM array packaged in a
14mm x 22mm 153 lead BGA.
The WED9LAPC2B16P8BC provides the memory required for the
BRAM (Buffer Memory) and PRAM (Pointer Memory) memory
ports for Lucent’s LUCTAPC640 ATM port controller. When used
in conjunction with the WED9LAPC2C16V4BC, which provides
memory for the CRAM (Control Memory) and VCRAM (Virtual
Control Memory) memory ports, the entire memory requirement of
the LUCTAPC640 can be met using these 2 BGA devices.
The WED9LAPC2B16P8BC is 100% tested to the timing require-
ments of the LUCTAPC640’s memory interface timing for both
Commercial and Industrial temperature ranges.
FIG. 1
PIN CONFIGURATION
PINOUT BRAM AND PRAM MCM -- TOP VIEW
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VCC
Bdata_a
Bdata_a
VSS
Bdata_a
Bdata_a
VCC
Bdata_b
Bdata_b
VSS
Bdata_b
Bdata_b
VCC
Pdata
Pdata
Pdata
Pdata
2
Bdata_a
Bdata_a
Bdata_a
Bdata_a
Bdata_a
Bdata_a
Bdata_b
Bdata_b
Bdata_b
Bdata_b
Bdata_b
Bdata_b
VCC
Pdata
VCC
VCC
Pdata
3
Bdata_a
Bdata_a
Bdata_a
Bdata_a
Bdata_a
Bdata_a
Bdata_b
Bdata_b
Bdata_b
Bdata_b
Bdata_b
Bdata_b
VSS
VSS
VSS
Pdata
Pdata
4
VSS
VSS
VCC
VCC
VCC
VSS
VSS
VSS
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VCC
VCC
5
GCLK
VSS
NC
VCC
VCC
VCC
VCC
VCC
NC
NC
NC
NC
NC
NC
NC
VCC
PCASN
6
VSS
NC
NC
VSS
VSS
VSS
VSS
NC
NC
NC
NC
NC
NC
NC
NC
VCC
PRASN
7
BWEN
VCC
VSS
VSS
VSS
VSS
VCC
VSS
VSS
VSS
VCC
VSS
VSS
VSS
VSS
PDQM
PWEN
8
BCASN
VCC
BADDR9
BADDR7
BADDR5
BADDR3
VCC
BADDR1
BADDR10
BADDR12
VCC
PADDR8
PADDR6
PADDR4
PADDR2
PADDR0
PBS
9
BRASN
BDQM
BADDR11
BADDR8
BADDR6
BADDR4
VCC
BADDR2
BADDR0
BADDR13
VCC
PADDR9
PADD7
PADDR5
PADDR3
PADDR1
PADDR10
September 2000 Rev. 0
ECO #13175
1
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
WED9LAPC2B16P8BC
FIG. 1
PIN CONFIGURATION (CONTINUED)
PIN DESCRIPTION
Pin Name
BRAM Address
BRAM Data
BRAM bank select
BRAM DQM
BRAM row address strobe
BRAM column address strobe
BRAM write enable
PRAM address
PRAM data
PRAM bank select
PRAM DQM
PRAM row address strobe
PRAM column address strobe
PRAM write enable
Global clock
Power supply
Ground
Description
Address pins for the SDRAM memory that serves as the buffer memory (BRAM)
Data I/O pins for the SDRAM buffer memory (BRAM)
Bank address pin for the SDRAM buffer memory (BRAM)
DQM (data mask) pin for the SDRAM buffer memory (BRAM)
RAS pin for the SDRAM buffer memory (BRAM)
CAS pin for the SDRAM buffer memory (BRAM)
Write enable pin for the SDRAM buffer memory (BRAM)
Address pins for the SDRAM memory that serves as the pointer memory (PRAM)
Data I/O pins for the SDRAM pointer memory (PRAM)
Bank address pin for the SDRAM pointer memory (PRAM)
DQM (data mask) pin for the SDRAM pointer memory (PRAM)
RAS pin for the SDRAM pointer memory (PRAM)
CAS pin for the SDRAM pointer memory (PRAM)
Write enable pin for the SDRAM pointer memory (PRAM)
Common clock pin for both the BRAM and PRAM memory arrays
Power supply pins
Ground pins
Symbol
BADDR
BDATA
BADDR12, BADDR13
BDQM
BRAS
BCAS
BWE
PADDR
Pdata
PBS
PDQM
PRAS
PCASN
PWE
GCLK
VCC
VSS
FIG. 2
BLOCK DIAGRAM 4M x 32 SDRAM / 2M x 8 SDRAM
BADDR0-11
BADDR12
BADDR13
BDQM
ADDR
BA0
BA1
LDQM
UDQM
RAS
CAS
WE
CLK
CKE
CS
ADDR
BA0
BA1
LDQM
UDQM
RAS
CAS
WE
CLK
1M x 16 x 4 SDRAM
DQ
0-7
Bdata
0-15
BRASN
BCASN
BWEN
GCLK
DQ
8-15
VCC
VSS
1M x 16 x 4 SDRAM
DQ
0-7
Bdata
16-31
DQ
8-15
PADDR0-10
ADDR0-10
1M x 8 x 2 SDRAM
PBS
PDQM
BA1
DQM
DQ
0-7
PRASN
PCASN
PWEN
RAS
CAS
WE
CLK
Pdata
0-7
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September 2000 Rev. 0
WED9LAPC2B16P8BC
ABSOLUTE MAXIMUM RATINGS
Voltage on Vcc Relative to Vss
Vin (DQx)
Storage Temperature (BGA)
Junction Temperature
Short Circuit Output Current
-0.5V to +4.6V
-0.5V to Vcc +0.5V
-55°C to +125°C
+125°C
50 mA
RECOMMENDED DC OPERATING CONDITIONS
(0°C
≤
T
A
≤
70°C; V
CC
= 3.3V
±5%
unless otherwise noted)
Parameter
Supply Voltage (1)
Input High Voltage (1,2)
Input Low Voltage (1,2)
Input Leakage Current
0
≤
V
IN
≤
Vcc
Output Leakage (Output Disabled)
0
≤
V
IN
≤
Vcc
Output High (I
OH
= -2mA) (1)
Output Low (I
OL
= 2mA) (1)
Symbol
V
CC
V
IH
V
IL
IL
I
ILo
V
OH
V
OL
Min
3.135
2.0
-0.3
-10
-10
2.4
—
Max
3.465
V
CC
+0.3
0.8
10
10
—
0.4
Units
V
V
V
µA
µA
V
V
*Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those indicated
in operational sections of this specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
NOTES:
1. All voltages referenced to Vss (GND).
2. Overshoot: V
IH
≤
+6.0V for t
≤
t
KC
/2
Underershoot: V
IL
≥
-2.0V for t
≤
t
KC
/2
DC ELECTRICAL CHARACTERISTICS
Description
Operating Current
Operating Current
Operating Current
Operating Current
Conditions
BRAM and PRAM active
BRAM active/PRAM inactive
BRAM inactive/PRAM active
BRAM inactive/PRAM inactive
Symbol
ICC1
ICC2
ICC3
ICC4
Typ
170
140
90
40
Max
210
160
110
60
Units
mA
mA
mA
mA
Notes
BGA CAPACITANCE
Description
Address Input Capacitance (1)
Input/Output Capacitance (DQ) (1)
Control Input Capacitance (1)
Clock Input Capacitance (1)
NOTE:
1. This parameter is sampled.
Conditions
T
A
= 25°C; f = 1MHz
T
A
= 25°C; f = 1MHz
T
A
= 25°C; f = 1MHz
T
A
= 25°C; f = 1MHz
Symbol
C
I
C
O
C
A
C
CK
Typ
5
8
5
4
Max
8
10
8
6
Units
pF
pF
pF
pF
September 2000 Rev. 0
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WED9LAPC2B16P8BC
SDRAM AC CHARACTERISTICS
Parameter
Clock Cycle Time (1)
CL = 3
CL = 2
Symbol
t
CC
t
CC
t
SAC
t
OH
t
CH
t
CL
t
SS
t
SH
t
SLZ
t
SHZ
t
RRD
t
RCD
t
RP
t
RAS
t
RC
t
RFC
t
CDL
t
RDL
t
BDL
t
CCD
Min
8
10
2.5
3
3
2
1
1
6
16
20
20
48
70
70
1
2
1
1
Max
1000
1000
6
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK
CLK
CLK
CLK
ea
ea
Clock to valid Output delay (1,2)
Output Data Hold Time (2)
Clock HIGH Pulse Width (3)
Clock LOW Pulse Width (3)
Input Setup Time (3)
Input Hold Time (3)
CLK to Output Low-Z (2)
CLK to Output High-Z
Row Active to Row Active Delay (4)
RAS to CAS Delay (4)
Row Precharge Time (4)
Row Active Time (4)
Row Cycle Time - Operation (4)
Row Cycle Time - Auto Refresh (4,8)
Last Data in to New Column Address Delay (5)
Last Data in to Row Precharge (5)
Last Data in to Burst Stop (5)
Column Address to Column Address Delay (6)
Number of Valid Output Data (7)
10,000
2
1
NOTES:
1. Parameters depend on programmed CAS latency.
2. If clock rise time is longer than 1ns (t
rise
/2 -0.5)ns should be added to the parameter.
3. Assumed input rise and fall time = 1ns. If t
rise
of t
fal
l are longer than 1ns. [(t
rise
= t
fall
)/2] - 1ns should
be added to the parameter.
4. The minimum number of clock cycles required is detemined by dividing the minimum time required
by the clock cycle time and then rounding up to the next higher integer.
5. Minimum delay is required to complete write.
6. All devices allow every cycle column address changes.
7. In case of row precharge interrupt, auto precharge and read burst stop.
8. A new command may be given t
RFC
after self-refresh exit.
CLOCK FREQUENCY AND LATENCY PARAMETERS
(Unit = number of clock)
Cycle Time
CAS
Latency
3
2
t
RC
70ns
9
7
t
RAS
48ns
6
5
t
RP
20ns
3
2
t
RRD
16ns
2
2
t
RCD
20ns
3
2
t
CCD
10ns
1
1
t
CDL
10ns
1
1
t
RDL
10ns
2
2
8.0ns
10.0ns
REFRESH CYCLE PARAMETERS
Parameter
Refresh Period (1,2)
Symbol
t
REF
Min
—
Max
32
Units
ms
NOTES:
1. 1024 cycles.
2. Any time that the Refresh Period has been exceeded, a minimum of two Auto
(CBR) Refresh commands must be given to "wake-up" the device.
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September 2000 Rev. 0
WED9LAPC2B16P8BC
SDRAM COMMAND TRUTH TABLE
BRAS or
PRAS
L
L
L
L
L
H
H
H
H
H
H
X
X
Single Bank
Precharge all Banks
Bank Activate
Write
Write with Auto Precharge
Read
Read with Auto Precharge
Burst Termination
No Operation
Data Write/Output Disable
Data Mask/Output Disable
BCAS or
PCAS
L
L
H
H
H
L
L
L
L
H
H
X
X
BWE or
PWE
L
H
L
L
H
L
L
L
H
L
H
X
X
BDQM or
PDQM
X
X
X
X
X
X
X
X
X
X
X
L
H
X
BA
X
BA
BA
BA
BA
BA
X
X
X
X
BADDR12,
BADDR13
or PBS
BADDR or
PADDR
FUNCTION
Mode Register Set
Auto Refresh (CBR)
Precharge
NOTES
OP CODE
X
L
H
Row Address
L
H
L
H
X
X
X
X
4
4
2
2
2
2
2
3
2
NOTES:
1. All of the SDRAM operations are defined by states of BWE or PWE, BRAS or PRAS, BCAS or PCAS, and BDQM or PDQM at the positive rising edge of the clock.
2. Bank Select (BADDR12, BADDR13, or PBS), if BADDR12, BADDR13, or PBS = 0 then bank A is selected, if BADDR12, BADDR13, or PBS = 1 then bank B is
selected.
3. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency.
4. The BDQM or PDQM has two functions for the data DQ Read and Write operations. During a Read cycle, when BDQM or PDQM goes high at a clock timing the data
outputs are disabled and become high impedance after a two clock delay. BDQM or PDQM also provides a data mask function for Write cycles. When it activates,
the Write operation at the clock is prohibited (zero clock latency).
September 2000 Rev. 0
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