Preliminary
GS8160EV18/32/36AT-350/333/300/250/225/200/150
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
• FT pin for user-configurable flow through or pipeline
operation
• Dual Cycle Deselect (DCD) operation
• 1.8 V +10%/–10% core power supply
• 1.8 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
1M x 18, 512K x 32, 512K x 36
18Mb Sync Burst SRAMs
Flow Through/Pipeline Reads
350 MHz–150 MHz
1.8 V V
DD
1.8 V I/O
on every cycle with no degradation of chip performance.
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode pin
low places the RAM in Flow Through mode, causing output
data to bypass the Data Output Register. Holding FT high
places the RAM in Pipeline mode, activating the rising-edge-
triggered Data Output Register.
DCD Pipelined Reads
The GS8160EV18/32/36AT is a DCD (Dual Cycle Deselect)
pipelined synchronous SRAM. SCD (Single Cycle Deselect)
versions are also available. DCD SRAMs pipeline disable
commands to the same degree as read commands. DCD RAMs
hold the deselect command for one full cycle and then begin
turning off their outputs just after the second rising edge of
clock.
Functional Description
Applications
The GS8160EV18/32/36AT is an 18,874,368-bit (16,777,216-
bit for x32 version) high performance synchronous SRAM
with a 2-bit burst address counter. Although of a type
originally developed for Level 2 Cache applications supporting
high performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Controls
Sleep Mode
Low power (Sleep mode) is attained through the assertion
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
(High) of the ZZ signal, or by stopping the clock (CK).
control inputs (ADSP, ADSC, ADV), and write control inputs
Memory data is retained during Sleep mode.
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
Core and Interface Voltages
and power down control (ZZ) are asynchronous inputs. Burst
The GS8160EV18/32/36AT operates on a 1.8 V power supply.
cycles can be initiated with either ADSP or ADSC inputs. In
All input are 1.8 V compatible. Separate output power (V
DDQ
)
Burst mode, subsequent burst addresses are generated
pins are used to decouple output noise from the internal circuits
internally and are controlled by ADV. The burst address
and are 1.8 V compatible.
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
Parameter Synopsis
-350
Pipeline
3-1-1-1
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
1.8
2.85
395
455
4.5
4.5
270
305
-333
2.0
3.0
370
430
4.7
4.7
250
285
-300
2.2
3.3
335
390
5.0
5.0
230
270
-250
2.3
4.0
280
330
5.5
5.5
210
240
-200
2.7
5.0
230
270
6.5
6.5
185
205
-150
3.3
6.7
185
210
7.5
7.5
170
190
Unit
ns
ns
mA
mA
ns
ns
mA
mA
Flow
Through
2-1-1-1
Rev: 1.00a 6/2003
1/24
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8160EV18/32/36AT-350/333/300/250/225/200/150
TQFP Pin Description
Symbol
A
0
, A
1
A
DQ
A
DQ
B
DQ
C
DQ
D
NC
BW
B
A
, B
B,
B
C
, B
D
CK
GW
E
1
E
2
E
3
G
ADV
ADSP, ADSC
ZZ
LBO
V
DD
V
SS
V
DDQ
Type
I
I
I/O
—
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Description
Address field LSBs and Address Counter preset Inputs
Address Inputs
Data Input and Output pins
No Connect
Byte Write—Writes all enabled bytes; active low
Byte Write Enable for DQ
A
, DQ
B
Data I/Os; active low
Clock Input Signal; active high
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
Chip Enable; active high
Chip Enable; active low
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
Linear Burst Order mode; active low
Core power supply
I/O and Core Ground
Output driver power supply
Rev: 1.00a 6/2003
5/24
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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