TISPPBL3
DUAL FORWARD-CONDUCTING P-GATE THYRISTORS
FOR ERICSSON MICROELECTRONICS SLICS
Copyright © 2001, Power Innovations Limited, UK
OCTOBER 2000 — REVISED FEBRUARY 2001
PROGRAMMABLE OVERVOLTAGE PROTECTION FOR ERICSSON MICROELECTRONICS
SUBSCRIBER LINE INTERFACE CIRCUITS, SLICS
G
Overvoltage Protection for listed SLICs:-
SLIC †§
PBL 3762A/2
PBL 3762A/4
PBL 3764A/4
PBL 3764A/6
PBL 3766
PBL 3766/6
PBL 3767
PBL 3767/6
PBL 3860A/1
PBL 3860A/6
PBL 386 10/2
PBL 386 11/2
PBL 386 14/2
PBL 386 15/2
PBL 386 20/2
PBL 386 21/2
PBL 386 30/2
PBL 386 40/2
PBL 386 50/2
PBL 386 61/2
PBL 386 65/2
PBL 387 10/1
TISPPBL3
D PACKAGE
(TOP VIEW)
ü
ü
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(Tip)
K1
NC
1
2
3
4
8
7
6
5
K1 (Tip)
A
A
(Ground)
(Ground)
MD6XANA
(Gate) G
(Ring) K2
K2 (Ring)
NC - No internal connection
Terminal typical application names shown in
parenthesis
device symbol
K1
K1
A
G1,G2
A
K2
K2
Terminals K1, K2 and A correspond to the alternative
line designators of T, R and G or A, B and C. The
negative protection voltage is controlled by the
voltage, V
GG,
applied to the G terminal.
SD6XAEA
G
§ See Applications Information for earlier SLIC types.
High Voltage Capability
Supports Battery Voltages Down to -150 V
Specified 2/10 Impulse Limiting Voltage
- Voltage-Time Envelope Guaranteed
- Full -40 °C to 85 °C Temperature Range
Feed-Through Package Connections
- Minimises Inductive Wiring Voltages .
G
Rated for International Surge Wave Shapes
WAVE SHAPE
2/10 µs
10/700 µs
10/1000 µs
STANDARD
GR-1089-CORE
ITU-T K.20, K.21, K.45
GR-1089-CORE
I
TSP
A
100
40
30
G
G
HOW TO ORDER
DEVICE
TISPPBL3
PACKAGE
D (8-pin Small-Outline)
CARRIER
Embossed Tape Reeled
ORDER AS
TISPPBL3DR
description
The TISPPBL3 is a dual forward-conducting buffered p-gate overvoltage protector. It is designed to protect
the Ericsson Microelectronics SLICs (Subscriber Line Interface Circuits) against overvoltages on the
telephone line caused by lightning, a.c. power contact and induction. The TISPPBL3 limits voltages that
exceed the referenced SLIC supply rail levels.
† Customers are advised to obtain the latest version of the relevant Ericsson Microelectronics SLIC information to verify, before placing orders,
that the information being relied on is current.
PRODUCT
INFORMATION
A Bourns Company
Information is current as of publication date. Products conform to specifications in accordance
with the terms of Power Innovations standard warranty. Production processing does not
necessarily include testing of all parameters.
1
TISPPBL3
DUAL FORWARD-CONDUCTING P-GATE THYRISTORS
FOR ERICSSON MICROELECTRONICS SLICS
OCTOBER 2000 — REVISED FEBRUARY 2001
The SLIC line driver section is typically powered by a negative voltage, V
Bat
, in the region of -10 V to -90 V.
The protector gate is connected to this negative supply. This references the protection (clipping) voltage to the
negative supply voltage. As the protection voltage will track the negative supply voltage the overvoltage stress
on the SLIC is minimised. The TISPPBL3 buffered gate design reduces the loading on the SLIC supply during
overvoltages caused by power cross and induction.
Positive overvoltages are clipped to ground by diode forward conduction. Negative overvoltages are initially
clipped close to the SLIC negative supply rail value. If sufficient current is available from the overvoltage, then
the protector will crowbar into a low voltage ground referenced on-state condition. As the overvoltage
subsides the high holding current of the crowbar prevents d.c. latchup.
These monolithic protection devices are fabricated in ion-implanted planar vertical power structures for high
reliability and in normal system operation they are virtually transparent. The TISPPBL3 has an 8-pin plastic
small-outline surface mount package, D suffix, and is a universal substitute for TISPPBL1D and TISPPBL2D
devices.
absolute maximum ratings, -40 °C
≤
T
A
≤
85 °C (unless otherwise noted)
RATING
Repetitive peak off-state voltage, V
GK
= 0, -40°C
≤
T
J
≤
85°C
Repetitive peak gate-cathode voltage, V
KA
= 0, -40°C
≤
T
J
≤
85°C
Non-repetitive peak on-state pulse current (see Notes 1 and 2)
10/1000 µs (Bellcore GR-1089-CORE, Issue 2, December 1997, Revision 1, Section 4)
5/310 µs (ITU-T K.20, K.21 & K.45, open-circuit voltage wave shape 10/700 µs)
2/10 µs (Bellcore GR-1089-CORE, Issue 2, December 1997, Revision 1, Section 4)
Non-repetitive peak on-state current, 50/60 Hz, T
A
= 25°C (see Notes 2 and 3)
100 ms
1s
5s
300 s
900 s
Non-repetitive peak gate current, 1/2 µs pulse, cathodes commoned (see Note 1)
Operating free-air temperature range
Junction temperature
Storage temperature range
I
GSM
T
A
T
J
T
stg
I
TSM
10
4.4
2.1
0.64
0.60
40
-40 to +85
-40 to +150
-65 to +150
A
°C
°C
°C
A
I
TSP
30
40
100
A
SYMBOL
V
DRM
V
GKRM
VALUE
-170
-160
UNIT
V
V
NOTES: 1. Initially the protector must be in thermal equilibrium with -40 °C
≤
T
J
≤
85 °C. The surge may be repeated after the device returns to
its initial conditions. Above 85 °C, derate linearly to zero at 150 °C lead temperature.
2. These non-repetitive rated currents are peak values for either polarity. The rated current values may be applied either to the Ring to
Ground or to the Tip to Ground terminal pairs. Additionally, both terminal pairs may have their rated current values applied
simultaneously (in this case the Ground terminal current will be twice the rated current value of an individual terminal pair).
3. Values for V
GG
= -120 V. For values at other voltages see Figure 4. Above 25 °C, derate linearly to zero at 150 °C lead temperature.
recommended operating conditions
SEE Figure 10
C1
R1a
R1b
Gate decoupling capacitor
Series resistance for GR-1089-CORE first-level and second-level surge survival
Series resistance for GR-1089-CORE first-level surge survival
Series resistance for ITU-T recommendation K.20, K.21 and K.45
MIN
100
40
25
10
Ω
TYP
220
MAX
UNIT
nF
PRODUCT
2
INFORMATION
TISPPBL3
DUAL FORWARD-CONDUCTING P-GATE THYRISTORS
FOR ERICSSON MICROELECTRONICS SLICS
OCTOBER 2000 — REVISED FEBRUARY 2001
electrical characteristics, -40 °C
≤
T
A
≤
85 °C (unless otherwise noted)
PARAMETER
I
D
V
(BO)
t
(BR)
V
F
V
FRM
t
FR
I
H
I
GKS
I
GAT
Off-state current
Breakover voltage
Breakdown time
Forward voltage
Peak forward recovery
voltage
Forward recovery time
Holding current
Gate reverse current
Gate reverse current,
on state
Gate reverse current,
I
GAF
I
GT
V
GT
C
AK
NOTE
forward conducting
state
Gate trigger current
Gate trigger voltage
Anode-cathode off-
state capacitance
I
T
= -5 A, t
p(g)
≥
20 µs, V
GG
= -50 V, T
A
= 25 °C
I
T
= -5 A, t
p(g)
≥
20 µs, V
GG
= -50 V, T
A
= 25 °C
f = 1 MHz, V
d
= 1 V, I
G
= 0, T
A
= 25 °C
(see Note 4)
V
D
= -3 V
V
D
= -50 V
5
2.5
110
60
mA
V
pF
pF
I
F
= 1 A, t
w
= 500 µs, V
GG
= -50 V, T
A
= 25 °C
-10
mA
V
D
= V
DRM
, V
GK
= 0
TEST CONDITIONS
T
J
= -40 °C
T
J
= 85 °C
MIN
TYP
MAX
-5
-50
-120
1
3
8
1
10000
-150
T
J
= -40 °C
T
J
= 85 °C
-5
-50
-1
UNIT
µA
µA
V
µs
V
V
µs
mA
µA
µA
mA
I
T
= -100 A, 2/10 generator, Figure 3 test circuit (See Figure 2)
I
T
= -100 A, 2/10 generator, Figure 3 test circuit
(See Figure 2)
I
F
= 5 A, t
w
= 500 µs
I
F
= 100 A, 2/10 generator, Figure 3 test circuit (See Figure 2)
I
F
= 100 A, 2/10 generator, Figure 3 test
circuit (See Figure 2)
I
T
= -1 A, di/dt = 1A/ms, V
GG
= -50 V,
V
GG
= V
GK
= V
GKRM
, V
KA
= 0
I
T
= -0.5 A, t
w
= 500 µs, V
GG
= -50 V, T
A
= 25 °C
V
F
> 5 V
V
F
> 1 V
V
(BR)
< -100 V
4: These capacitance measurements employ a three terminal capacitance bridge incorporating a guard circuit. The unmeasured
device terminals are a.c. connected to the guard terminal of the bridge.
thermal characteristics
PARAMETER
R
θ
JA
Junction to free air thermal resistance
TEST CONDITIONS
P
tot
= 0.8 W, T
A
= 25 °C, 5
cm
2
,
FR4 PCB
MIN
TYP
MAX
160
UNIT
°C/W
PRODUCT
INFORMATION
3
TISPPBL3
DUAL FORWARD-CONDUCTING P-GATE THYRISTORS
FOR ERICSSON MICROELECTRONICS SLICS
OCTOBER 2000 — REVISED FEBRUARY 2001
PARAMETER MEASUREMENT INFORMATION
PRINCIPAL TERMINAL V-I CHARACTERISTIC
+i
I
FSP
(= |I
TSP
|)
Quadrant I
Forward
Conduction
Characteristic
GATE TRANSFER
CHARACTERISTIC
+i
K
I
FSM
(= |I
TSM
|)
I
F
V
F
V
GK(BO)
V
GG
(Circuit V
B
)
I
F
-v
V
D
I
D
I
GT
+v
-i
G
I
GAF
+i
G
I
(BO)
I
S
I
H
V
T
I
T
I
TSM
I
G
I
GAT
I
T
V
(BO)
V
S
Quadrant III
Switching
Characteristic
I
TSP
-i
PM6XAIB
I
K
-i
K
Figure 1 PRINCIPAL TERMINAL AND GATE TRANSFER CHARACTERISTICS
PROTECTOR MAXIMUM LIMITING VOLTAGE
vs
TIME
10
5
0
VOLTAGE - V
1 µs
10 ms
Time
1 µs
V
GG
= V
B
= -50 V
MAX V
FRM
= 8 V
-50
-60
-70
MAX V
(BO)
= -70 V
-80
PM6XALB
Figure 2 TRANSIENT LIMITS FOR TISPPBL3 2/10 IMPULSE LIMITING VOLTAGE
PRODUCT
4
INFORMATION
TISPPBL3
DUAL FORWARD-CONDUCTING P-GATE THYRISTORS
FOR ERICSSON MICROELECTRONICS SLICS
OCTOBER 2000 — REVISED FEBRUARY 2001
PARAMETER MEASUREMENT INFORMATION
IMPULSE
R1 CURRENT
40
Ω
I
T
, I
F
LIMITING
VOLTAGE
V
K
, V
F
Th4
DUT
(TISPPBL3)
Hi
ECAT WITH E505
2/10 OUTPUT NETWORK
Lo
Th5
R1 = ONE SECTION OF A BOURNS
4B04B-CS0-400 THICK-FILM
HIGH VOLTAGE PULSE
RESISTOR NETWORK
I
G
V
B
(V
GG
)
-50 V
AI6XBACC
220 nF
Figure 3 TEST CIRCUIT FOR MEASUREMENT OF LIMITING VOLTAGE
THERMAL INFORMATION
PEAK NON-RECURRING AC
vs
CURRENT DURATION
20
I
TSM
— Peak Non-Recurrent 50 Hz Current — A
15
10
8
7
6
5
4
3
2
1.5
1
0.8
0.7
0.6
0.5
0.01
TI61AF
RING AND TIP TERMINALS:
Equal I
TSM
values applied
simultaneously
GROUND TERMINAL:
Current twice I
TSM
value
EIA /JESD51
Environment and
PCB, T
A
= 25 °C
V
GG
= -80 V
V
GG
= -60 V
V
GG
= -100 V
V
GG
= -120 V
0.1
1
10
100
t — Current Duration — s
1000
Figure 4
PRODUCT
INFORMATION
5
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