CXR702080
CMOS 32-bit Single Chip Microcomputer
Description
The CXR702080 is a CMOS 32-bit microcomputer
integrating on a single chip an A/D converter, serial
interface, timer, bus interface unit, DMA controller,
memory stick interface, and as well as basic
configurations like a 32-bit RISC CPU, ROM, RAM,
and I/O port.
This also provides the idle/sleep/stop functions that
enable lower power consumption.
Features
•
CPU
•
Minimum instruction cycle
•
Incorporated ROM
•
Incorporated RAM
•
Peripheral functions
— Bus interface unit
— DMA controller
— A/D converter
— Serial interface
176 pin LFLGA (Plastic)
SR11 series 32-bit RISC CPU core
54.3ns (f
SRC
: 18.432MHz)
30.5µs (f
TEX
: 32.768kHz)
256K bytes
16K bytes
— Timers
4 channels
8-bit 4-analog input, successive approximation system
Clock synchronization, 2 channels
Clock synchronization, 1 channel (Incorporated 64-byte buffer RAM)
Asynchronization, 2 channels
8-bit timer, 8 channels
16-bit capture timer, 3 channels
8-bit time-base timer
Clock prescaler
16-bit watchdog timer
— Memory stick interface
— Beep output circuit
— External interruption
•
Standby mode
•
Package
Structure
Silicon gate CMOS IC
11 channels (polarity selection and both edge detection possible)
Idle/sleep/stop
176-pin plastic LFLGA
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E01701A22-PS
AV
DD
AV
REF
AV
SS
MSINS
INT0
to INT9
TDO
TRST
RTCK
TCK
TMS
TDI
10
∗
1
24
16
8
AN0
to AN3
4
A/D CONVERTER
CLOCK GENERATOR/
SYSTEM CONTROLLER
EXTERNAL BUS
SCS1
SI1
SO1
SCK1
BUS INTERFACE UNIT
SERIAL INTERFACE
UNIT (CH1)
ROM
256K BYTES
ARM7TDMI
CPU CORE
SCS0
SI0
SO0
SCK0
SERIAL INTERFACE
UNIT (CH0)
RAM
TXOUT
TX
TEX
XOUT
XTAL
EXTAL
RST
V
DD
V
SS
Block Diagram
19
8
2
TxD0
RxD0
2
∗
2
6
3
∗
1
∗
2
RAM
16K BYTES
UART (CH0)
2
∗
2
DMAC (CH0)
DMAC (CH1)
DMAC (CH2)
DMAC (CH3)
8
∗
1
16-BIT CAPTURE TIMER (CH0)
WATCHDOG TIMER
16-BIT CAPTURE TIMER (CH1)
TOKEI PRESCALER
16-BIT CAPTURE TIMER (CH2)
INTERRUPT CONTROLLER
SCS2
SI2
SO2
SCK2
SERIAL INTERFACE
UNIT (CH2)
A0
to A23
D0
to D15
CS0
to CS7
RD
WE
LWR/LB
UWR/UB
WAIT
MA0
to MA18
MD0
to MD7
MCS0,
MCS1
MRD
MWE
DACK0
DREQ0
DACK1
DREQ1
TxD1
RxD1
UART (CH1)
–2–
6
8
6
4
8
6
6
4
8
MSBS
MSDIO
MSIDR
MSSCLK
EC0
MEMORY STICK INTERFACE
8-BIT TIMER/COUNTER (CH0)
T1
EC2
8-BIT TIMER (CH1)
8-BIT TIMER/COUNTER (CH2)
T3
8-BIT TIMER (CH3)
8-BIT TIMER (CH4)
CT0ED0
CT0ED1
CT1ED0
CT1ED1
CT2ED0
CT2ED1
BEEP
8-BIT TIMER (CH5)
8-BIT TIMER (CH6)
PORT A PORT B PORT C PORT D PORT E PORT F PORT G PORT H PORT I
PORT J PORT K PORT L PORT M PORT N PORT O
8-BIT TIMER (CH7)
8
8
7
3
8
4
CXR702080
∗
1
The number of causes of interrupts generated from the module is as shown. But the number of causes input to the interrupt controller differs from the shown becauses of OR.
∗
2
A part of the interrupt signals generated from UART, MEMORY STICK INTERFACE is input to the interrupt controller via DMA depending on applications.
NXP MCU
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