DATASHEET
KAD5510P-50
10-Bit, 500MSPS A/D Converter
The
KAD5510P-50
is a low-power, high performance, 10-bit,
500MSPS analog-to-digital converter designed with Intersil’s
proprietary FemtoCharge™ technology on a standard CMOS
process. The KAD5510P-50 is part of a pin-compatible
portfolio of 10, 12 and 14-bit A/Ds with sample rates ranging
from 125MSPS to 500MSPS.
The device utilizes two time-interleaved 10-bit, 250MSPS A/D
cores to achieve the ultimate sample rate of 500MSPS. A
single 500MHz conversion clock is presented to the converter,
and all interleave clocking is managed internally.
A Serial Peripheral Interface (SPI) port allows for extensive
configurability, as well as fine control of matching
characteristics (gain, offset, skew) between the two converter
cores. These adjustments allow the user to minimize spurs
associated with the interleaving process.
Digital output data is presented in selectable LVDS or CMOS
formats. The KAD5510P-50 is available in a 72 Ld QFN
package with an exposed paddle. Performance is specified
over the full industrial temperature range (-40°C to +85°C).
FN6811
Rev 3.00
May 31, 2016
Features
• Programmable gain, offset and skew control
• 1.3GHz analog input bandwidth
• 60fs clock jitter
• Over-range indicator
• Selectable clock divider: ÷1 or ÷2
• Clock phase selection
• Nap and sleep modes
• Two’s complement, gray code or binary data format
• DDR LVDS-compatible or LVCMOS outputs
• Programmable built-in test patterns
• Single-supply 1.8V operation
• Pb-free (RoHS compliant)
Applications
• Radar and satellite antenna array processing
• Broadband communications
• High-performance data acquisition
Key Specifications
• SNR = 60.7dBFS for f
IN
= 105MHz (-1dBFS)
• SFDR = 83.2dBc for f
IN
= 105MHz (-1dBFS)
• Power consumption = 414mW
CLKDIV
CLKP
CLKN
OVDD
AVDD
CLOCK GENERATION
AND
INTERLEAVE CONTROL
CLKOUTP
CLKOUTN
SHA
10-BIT
250 MSPS
ADC
VREF
D[9:0]P
D[9:0]N
ORP
DIGITAL
ERROR
CORRECTION
VINP
VINN
ORN
OUTFMT
OUTMODE
VCM
SHA
10-BIT
250 MSPS
ADC
VREF
1.25V
+
–
SPI
CONTROL
RESETN
NAPSLP
AGND
FIGURE 1. BLOCK DIAGRAM
FN6811 Rev 3.00
May 31, 2016
OGND
CSB
SCLK
SDIO
SDO
Page 1 of 30
KAD5510P-50
Table of Contents
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin-Compatible Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Digital Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Switching Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-On Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
User Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Over-Range Indicator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Nap/Sleep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Indexed Device Configuration/Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Global Device Configuration/Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
14
14
15
15
16
16
17
17
17
17
17
18
20
20
21
21
21
22
23
Equivalent Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
ADC Evaluation Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Split Ground and Power Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Input Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Exposed Paddle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bypass and Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LVDS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LVCMOS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
26
26
26
26
26
26
27
27
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
FN6811 Rev 3.00
May 31, 2016
Page 2 of 30
KAD5510P-50
Ordering Information
PART NUMBER
(Notes
1, 2)
KAD5510P-50Q72
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate -
e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. For Moisture Sensitivity Level (MSL), please see product information page for
KAD5510P-50.
For more information on MSL, please see tech brief
TB363.
PART MARKING
KAD5510P-50 Q72EP-I
SPEED
(MSPS)
500
TEMP. RANGE
(°C)
-40 to +85
PACKAGE
(RoHS Compliant)
72 Ld QFN
PKG.
DWG. #
L72.10x10D
Pin-Compatible Family
MODEL
KAD5514P-25
KAD5514P-21
KAD5514P-17
KAD5514P-12
KAD5512P-50
KAD5512P-25, KAD5512HP-25
KAD5512P-21, KAD5512HP-21
KAD5512P-17, KAD5512HP-17
KAD5512P-12, KAD5512HP-12
KAD5510P-50
RESOLUTION
14
14
14
14
12
12
12
12
12
10
SPEED
(MSPS)
250
210
170
125
500
250
210
170
125
500
FN6811 Rev 3.00
May 31, 2016
Page 3 of 30
KAD5510P-50
Absolute Maximum Ratings
AVDD to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V
OVDD to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V
AVSS to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
Analog Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Clock Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Logic Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Logic Inputs to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Thermal Information
Thermal Resistance (Typical,
Note 3)
JA
(°C/W)
72 Ld QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see
TB493
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTE:
3.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379
for details.
Electrical Specifications
All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
T
A
= -40°C to +85°C (typical specifications at +25°C), A
IN
= -1dBFS, f
SAMPLE
= 500MSPS.
KAD5510P-50
PARAMETER
DC SPECIFICATIONS
Analog Input
Full-Scale Analog Input Range
Input Resistance
Input Capacitance
Full-Scale Range Temperature Drift
Input Offset Voltage
Gain Error
Common-Mode Output Voltage
Clock Inputs
Inputs Common-Mode Voltage
CLKP, CLKN Input Swing
Power Requirements
1.8V Analog Supply Voltage
1.8V Digital Supply Voltage
1.8V Analog Supply Current
1.8V Digital Supply Current (Note
5)
Power Supply Rejection Ratio
Total Power Dissipation
Normal Mode
Nap Mode
Sleep Mode
Nap Mode Wakeup Time (Note
6)
Sleep Mode Wakeup Time (Note
6)
AC SPECIFICATIONS (Notes
7, 8)
Differential Nonlinearity
Integral Nonlinearity
DNL
INL
-0.5
-0.75
±0.1
±0.2
0.5
0.75
LSB
LSB
P
D
P
D
P
D
CSB at logic high
Sample Clock Running
Sample Clock Running
3mA LVDS
414
148
2
1
1
438
170.2
6
mW
mW
mW
µs
ms
AVDD
OVDD
I
AVDD
I
OVDD
PSRR
3mA LVDS
30MHz, 200mV
P-P
1.7
1.7
1.8
1.8
171
58
-36
1.9
1.9
188
65
V
V
mA
mA
dB
.9
1.8
V
V
V
FS
R
IN
C
IN
A
VTC
V
OS
E
G
V
CM
435
Differential
Differential
Differential
Full Temperature
-10
1.40
1.47
500
1.9
90
±2
±2
535
635
10
1.54
V
P-P
Ω
pF
ppm/°C
mV
%
mV
SYMBOL
TEST CONDITIONS
MIN
(Note
4)
TYP
MAX
(Note
4)
UNIT
FN6811 Rev 3.00
May 31, 2016
Page 4 of 30
KAD5510P-50
Electrical Specifications
All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
T
A
= -40°C to +85°C (typical specifications at +25°C), A
IN
= -1dBFS, f
SAMPLE
= 500MSPS. (Continued)
KAD5510P-50
PARAMETER
Minimum Conversion Rate (Note
9)
Maximum Conversion Rate
Signal-to-Noise Ratio
SYMBOL
f
S
MIN
f
S
MAX
SNR
f
IN
= 10MHz
f
IN
= 105MHz
f
IN
= 190MHz
f
IN
= 364MHz
f
IN
= 695MHz
f
IN
= 995MHz
Signal-to-Noise and Distortion
SINAD
f
IN
= 10MHz
f
IN
= 105MHz
f
IN
= 190MHz
f
IN
= 364MHz
f
IN
= 695MHz
f
IN
= 995MHz
Effective Number of Bits
ENOB
f
IN
= 10MHz
f
IN
= 105MHz
f
IN
= 190MHz
f
IN
= 364MHz
f
IN
= 695MHz
f
IN
= 995MHz
Spurious-Free Dynamic Range
SFDR
f
IN
= 10MHz
f
IN
= 105MHz
f
IN
= 190MHz
f
IN
= 364MHz
f
IN
= 695MHz
f
IN
= 995MHz
Intermodulation Distortion
IMD
f
IN
= 70MHz
f
IN
= 170MHz
Word Error Rate
Full Power Bandwidth
NOTES:
4. Parameters with MIN and/or MAX limits are 100% production tested at their worst case temperature extreme (+85°C).
5. Digital Supply Current is dependent upon the capacitive loading of the digital outputs. I
OVDD
specifications apply for 10pF load on each digital output.
6. See
“Nap/Sleep” on page 17
for more details.
7. AC Specifications apply after internal calibration of the ADC is invoked at the given sample rate and temperature. Refer to
“Power-On Calibration” on
page 14
and
“User Initiated Reset” on page 15
for more detail.
8. SFDR, SINAD and ENOB specifications apply after gain error and timing skew between ADC cores have been minimized through external calibration.
9. The DLL Range setting must be changed for low speed operation. See
Table 15 on page 23
for more detail.
WER
FPBW
70
9.6
59.3
59.5
500
60.7
60.7
60.6
60.5
59.9
59.0
60.7
60.6
60.5
60.4
57.5
49.3
9.8
9.8
9.8
9.7
9.3
7.9
83.2
83.2
80.6
75.7
61.0
49.1
-91.0
-90.3
10
-12
1.3
GHz
TEST CONDITIONS
MIN
(Note
4)
TYP
MAX
(Note
4)
80
UNIT
MSPS
MSPS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
Bits
Bits
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
FN6811 Rev 3.00
May 31, 2016
Page 5 of 30
DSP and ARM Processors
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