ZL2005PALRFT1 datasheet, PDF - EEWORLD Datasheet

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ZL2005PALRFT1: DescriptionDigital-DC™ Controller with Drivers and POLA/DOSA Trim; QFN36; Temp Range: -40° to 85°C; CategoryPower/power management The power supply circuit; File Size2MB，41 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/

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ZL2005PALRFT1 Overview

Digital-DC™ Controller with Drivers and POLA/DOSA Trim; QFN36; Temp Range: -40° to 85°C

ZL2005PALRFT1 Parametric

Parameter Name	Attribute value
Brand Name	Intersil
Maker	Renesas Electronics Corporation
Parts packaging code	QFN
package instruction	HVQCCN, LCC36,.25SQ,20
Contacts	36
Reach Compliance Code	compliant
ECCN code	EAR99
Factory Lead Time	9 weeks
Other features	OUTPUT VOLTAGE IS ADJUSTABLE FROM 0.54 TO 5.5V
Analog Integrated Circuits - Other Types	SWITCHING CONTROLLER
control mode	VOLTAGE-MODE
Control Technology	PULSE WIDTH MODULATION
Maximum input voltage	14 V
Minimum input voltage	3 V
Nominal input voltage	12 V
JESD-30 code	S-XQCC-N36
JESD-609 code	e3
length	6 mm
Humidity sensitivity level	2
Number of functions	1
Number of terminals	36
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	UNSPECIFIED
encapsulated code	HVQCCN
Encapsulate equivalent code	LCC36,.25SQ,20
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1 mm
surface mount	YES
Switch configuration	PUSH-PULL
Maximum switching frequency	1400 kHz
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	6 mm
Base Number Matches	1

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ZL2005P

NOT RECOMMENDED FOR NEW DESIGNS

RECOMMENDED REPLACEMENT PART

ZL6100

DATASHEET

FN6849

Rev 3.00

December 16, 2011

Digital-DC™ Controller with Drivers and POLA/DOSA Trim

Description

The ZL2005P is an innovative mixed-signal power

conversion and management IC that combines a com-

pact, efficient, synchronous DC-DC buck controller,

adaptive drivers and key power and thermal manage-

ment functions in one IC, providing flexibility and

scalability while decreasing board space requirements

and design complexity. Zilker Labs Digital-DC tech-

nology enables a unique blend of performance and

features not available in either traditional analog or

newer digital approaches, resolving the issues associ-

ated with providing multiple low-voltage power

domains on a single PCB.

The ZL2005P is designed to be configured either as a

standard ZL2005 or as POLA/DOSA compatible

device.

All operating features can be configured by simple

pin-strap selection, resistor selection or through the

on-board serial port. The PMBus™-compliant

ZL2005P uses the SMBus™ serial interface for com-

munication with other Digital-DC products or a host

controller.

Features Power Conversion

• Efficient synchronous buck controller

• 3 V to 14 V input range

• 0.54 V to 5.5 V output range (with margin)

• Optional output voltage setting with VADJ pin

• ± 1% output accuracy

• Internal 3 A drivers support >40 A power stage

• Fast load transient response

• Phase interleaving

• RoHS compliant (6 x 6 mm) QFN package

Power Management

• Digital soft start/stop

• Precision delay and ramp-up

• Voltage tracking, sequencing and margining

• Voltage/current/temperature monitoring

• I

C/SMBus communication

• Output overvoltage and overcurrent protection

• Internal non-voltatile memory (NVM)

• PMBus compliant

Applications

•

Servers/storage equipment

Telecom/datacom equipment

Power supplies (memory, DSP, ASIC, FPGA)

DLY FC ILIM

EN PG (0,1) (0,1) (0,1) CFG UVLO V25 VR VDD

SS (0,1)

VTRK

MGN

SYNC

VADJ

POWER

MANAGEMENT

LDO

BST

ISENA

ISENB

DRIVER

NON-

VOLATILE

MEMORY

PWM

CONTROLLER

CURRENT

SENSE

TEMP

SENSOR

SCL

SDA

SALRT

MONITOR

ADC

SA (0,1)

XTEMP VSEN

PGND SGND DGND

Figure 1. Block Diagram

FN6849 Rev 3.00

December 16, 2011

Page 1 of 41

ZL2005P

Table of Contents

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Typical Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ZL2005P Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1

Digital-DC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2

ZL2005 - ZL2005P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3

Power Conversion Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4

Power Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5

Multi-mode Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Conversion Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1

Internal Bias Regulators and Input Supply Connections . . . . . . . . . . . . . . . . . . . . .

5.2

High-side Driver Boost Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3

Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4

Start-up Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.5

Soft Start Delay and Ramp Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6

Power Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7

Switching Frequency and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.8

Selecting Power Train Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.9

Current Limit Threshold Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.10 Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.11 Non-Linear Response Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.12 Efficiency Optimized Driver Dead-time Control . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Management Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1

Input Undervoltage Lockout (UVLO) Standard Mode . . . . . . . . . . . . . . . . . . . . . . . .

6.2

Output Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3

Output Pre-Bias Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.4

Output Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.5

Thermal Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.6

Voltage Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.7

Voltage Margining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.8

C/SMBus Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.9

C/SMBus Device Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.10 Phase Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.11 Output Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.12 Monitoring via I

C/SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.13 Temperature Monitoring Using the XTEMP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.14 Non-volatile Memory and Device Security Features . . . . . . . . . . . . . . . . . . . . . . . .

Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.1

Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.2

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

FN6849 Rev 3.00

December 16, 2011

Page 2 of 41

ZL2005PALRFT1 Related Products

	ZL2005PALRFT1	ZL2005PALRFT
Description	Digital-DC™ Controller with Drivers and POLA/DOSA Trim; QFN36; Temp Range: -40° to 85°C	Digital-DC™ Controller with Drivers and POLA/DOSA Trim; QFN36; Temp Range: -40° to 85°C
Brand Name	Intersil	Intersil
Maker	Renesas Electronics Corporation	Renesas Electronics Corporation
Parts packaging code	QFN	QFN
package instruction	HVQCCN, LCC36,.25SQ,20	HVQCCN, LCC36,.25SQ,20
Contacts	36	36
Reach Compliance Code	compliant	compliant
ECCN code	EAR99	EAR99
Factory Lead Time	9 weeks	9 weeks
Other features	OUTPUT VOLTAGE IS ADJUSTABLE FROM 0.54 TO 5.5V	OUTPUT VOLTAGE IS ADJUSTABLE FROM 0.54 TO 5.5V
Analog Integrated Circuits - Other Types	SWITCHING CONTROLLER	SWITCHING CONTROLLER
control mode	VOLTAGE-MODE	VOLTAGE-MODE
Control Technology	PULSE WIDTH MODULATION	PULSE WIDTH MODULATION
Maximum input voltage	14 V	14 V
Minimum input voltage	3 V	3 V
Nominal input voltage	12 V	12 V
JESD-30 code	S-XQCC-N36	S-XQCC-N36
JESD-609 code	e3	e3
length	6 mm	6 mm
Humidity sensitivity level	2	2
Number of functions	1	1
Number of terminals	36	36
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Package body material	UNSPECIFIED	UNSPECIFIED
encapsulated code	HVQCCN	HVQCCN
Encapsulate equivalent code	LCC36,.25SQ,20	LCC36,.25SQ,20
Package shape	SQUARE	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260	260
Certification status	Not Qualified	Not Qualified
Maximum seat height	1 mm	1 mm
surface mount	YES	YES
Switch configuration	PUSH-PULL	PUSH-PULL
Maximum switching frequency	1400 kHz	1400 kHz
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed
Terminal form	NO LEAD	NO LEAD
Terminal pitch	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD
Maximum time at peak reflow temperature	30	30
width	6 mm	6 mm

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