CY7C1386CV25-167BGI datasheet, PDF

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CY7C1386CV25-167BGI: DescriptionCache SRAM, 512KX36, 3.4ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119; Categorystorage storage; File Size550KB，36 Pages; ManufacturerCypress Semiconductor

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CY7C1386CV25-167BGI Overview

Cache SRAM, 512KX36, 3.4ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119

CY7C1386CV25-167BGI Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Cypress Semiconductor
Parts packaging code	BGA
package instruction	14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
Contacts	119
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	3.4 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	167 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B119
JESD-609 code	e0
length	22 mm
memory density	18874368 bit
Memory IC Type	CACHE SRAM
memory width	36
Number of functions	1
Number of terminals	119
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	512KX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA119,7X17,50
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	225
power supply	2.5 V
Certification status	Not Qualified
Maximum seat height	2.4 mm
Maximum standby current	0.03 A
Minimum standby current	2.38 V
Maximum slew rate	0.18 mA
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN LEAD
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	14 mm
Base Number Matches	1

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CY7C1386CV25

CY7C1387CV25

18-Mb (512K x 36/1M x 18) Pipelined DCD

Sync SRAM

Features

• Supports bus operation up to 250 MHz

• Available speed grades are 250, 225, 200 and 167 MHz

• Registered inputs and outputs for pipelined operation

• Optimal for performance (Double-Cycle deselect)

• Depth expansion without wait state

• 2.5V + 5% power supply (V

)

• Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

— 2.8 ns (for 225-MHz device)

— 3.0 ns (for 200-MHz device)

— 3.4 ns (for 167-MHz device)

• Provide high-performance 3-1-1-1 access rate

•

User-selectable burst counter supporting Intel



Pentium interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

• Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA

and 165-Ball fBGA packages

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• “ZZ” Sleep Mode Option

Functional Description

[1]

The CY7C1386CV25/CY7C1387CV25 SRAM integrates

524,288 x 36 and 1048,576 x 18 SRAM cells with advanced

synchronous peripheral circuitry and a two-bit counter for

internal burst operation. All synchronous inputs are gated by

registers controlled by a positive-edge-triggered Clock Input

(CLK). The synchronous inputs include all addresses, all data

inputs,

address-pipelining

Chip

Enable

(CE

depth-expansion Chip Enables (CE

and CE

3[2]

), Burst

Control inputs (ADSC, ADSP, and ADV), Write Enables (BW

and BWE), and Global Write (GW). Asynchronous inputs

include the Output Enable (OE) and the ZZ pin.

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to four bytes wide as

controlled by the byte write control inputs. GW active LOW

causes all bytes to be written. This device incorporates an

additional pipelined enable register which delays turning off

the output buffers an additional cycle when a deselect is

executed.This feature allows depth expansion without penal-

izing system performance.

The CY7C1386CV25/CY7C1387CV25 operates from a +2.5V

power supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

Selection Guide

250 MHz

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

2.6

350

225 MHz

2.8

325

200 MHz

3.0

300

167 MHz

3.4

275

Unit

Shaded areas contain advance information.

Please contact your local Cypress sales representative for availability of these parts.

Notes:

1. For best–practices recommendations, please refer to the Cypress application note

System Design Guidelines

on www.cypress.com.

2. CE

and CE

are for TQFP and 165 fBGA package only. 119 BGA is offered only in Single Chip Enable.

Cypress Semiconductor Corporation

Document #: 38-05242 Rev. *A

•

3901 North First Street

•

San Jose

CA 95134

•

408-943-2600

Revised February 26, 2004

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