Z8018008VSG datasheet, PDF - EEWORLD Datasheet

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Z8018008VSG: DescriptionMicrocontroller, 8-Bit, 8MHz, CMOS, PQCC68, LCC-68; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，124 Pages; ManufacturerIXYS; Environmental Compliance

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Z8018008VSG Overview

Microcontroller, 8-Bit, 8MHz, CMOS, PQCC68, LCC-68

Z8018008VSG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IXYS
Parts packaging code	LCC
package instruction	QCCJ, LDCC68,1.0SQ
Contacts	68
Reach Compliance Code	compliant
Has ADC	NO
Other features	DYNAMIC REFRESH CONTROL; 1M BYTE PHYSICAL MEMORY
Address bus width	20
bit size	8
boundary scan	NO
maximum clock frequency	8 MHz
DAC channel	NO
DMA channel	YES
External data bus width	8
Format	FIXED POINT
Integrated cache	NO
JESD-30 code	S-PQCC-J68
JESD-609 code	e3
length	24.2316 mm
low power mode	YES
Number of DMA channels	2
Number of external interrupt devices	4
Number of I/O lines
Number of serial I/Os	3
Number of terminals	68
Number of timers	2
On-chip data RAM width
On-chip program ROM width
Maximum operating temperature	70 °C
Minimum operating temperature
PWM channel	NO
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC68,1.0SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	260
power supply	5 V
Certification status	Not Qualified
RAM (number of words)	0
rom(word)	0
Maximum seat height	4.57 mm
speed	8 MHz
Maximum slew rate	50 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	24.2316 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER
Base Number Matches	1

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Z80180

Microprocessor Unit

Product Specification

PS014001-0801

Z80180

Microprocessor Unit

iii

Table of Contents

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Multiplexed Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . 15

Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . .

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ASCI Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ASCI Transmit Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . .

Channel 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ASCI Receive Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Channel 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PS014001-0801

Table of Contents

Z80180

Microprocessor Unit

DMA Memory Address Register Channel 1 . . . . . . . . . . . . . . . . 83

DMA Memory Address Register, Channel 1L . . . . . . . . . . . 84

DMA Memory Address Register, Channel 1H . . . . . . . . . . . 84

DMA I/O Address Register Channel 1 . . . . . . . . . . . . . . . . . . . . 85

DMA I/O Address Register Channel 1L . . . . . . . . . . . . . . . . 86

DMA I/O Address Register Channel 1H . . . . . . . . . . . . . . . . 86

DMA I/O Address Register Channel 1B . . . . . . . . . . . . . . . . 87

DMA Status Register (DSTAT) . . . . . . . . . . . . . . . . . . . . . . 87

Mnemonic DSTAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

DMA Mode Register (DMODE) . . . . . . . . . . . . . . . . . . . . . . 89

Mnemonic DMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

DMA/WAIT Control Register (DCNTL) . . . . . . . . . . . . . . . . . . . . 92

Interrupt Vector Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Mnemonic: IL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Int/TRAP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Mnemonics ITC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Refresh Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Mnemonic RCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

MMU Common Base Register . . . . . . . . . . . . . . . . . . . . . . . . . 101

Mnemonic CBR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

MMU Bank Base Register (BBR) . . . . . . . . . . . . . . . . . . . . . . . 102

Mnemonic BBR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

MMU Common/Bank Area Register (CBAR) . . . . . . . . . . . . . . 103

Mnemonic CBAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Operation Mode Control Register . . . . . . . . . . . . . . . . . . . . . . 104

Mnemonic OMCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

I/O Control Register (ICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Table of Contents

PS014001-0801

Z8018008VSG Related Products

	Z8018008VSG	Z8018006PSG	Z8018008PSG	Z8018006FSG	Z8018008FSG	Z8018006FSC	Z8018006VSG	Z8018008FSC	Z8018008PSC	Z8018006PSC
Description	Microcontroller, 8-Bit, 8MHz, CMOS, PQCC68, LCC-68	Microcontroller, 8-Bit, 6MHz, CMOS, PDIP64, PLASTIC, DIP-64	Microcontroller, 8-Bit, 8MHz, CMOS, PDIP64, PLASTIC, DIP-64	Microcontroller, 8-Bit, 6MHz, CMOS, PQFP80, PLASTIC, QFP-80	Microcontroller, 8-Bit, 8MHz, CMOS, PQFP80, QFP-80	Microprocessor, 8-Bit, 6MHz, CMOS, PQFP80, PLASTIC, QFP-80	Microcontroller, 8-Bit, 6MHz, CMOS, PQCC68, LCC-68	Microprocessor, 8-Bit, 8MHz, CMOS, PQFP80, PLASTIC, QFP-80	Microprocessor, 8-Bit, 8MHz, CMOS, PDIP64, PLASTIC, DIP-64	Microprocessor, 8-Bit, 6MHz, CMOS, PDIP64, PLASTIC, DIP-64
Is it lead-free?	Lead free	Lead free	Lead free	Lead free	Lead free	Contains lead	Lead free	Contains lead	Contains lead	Contains lead
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to	incompatible	conform to	incompatible	incompatible	incompatible
Parts packaging code	LCC	DIP	DIP	QFP	QFP	QFP	LCC	QFP	DIP	DIP
package instruction	QCCJ, LDCC68,1.0SQ	PLASTIC, DIP-64	PLASTIC, DIP-64	PLASTIC, QFP-80	QFP,	PLASTIC, QFP-80	LCC-68	PLASTIC, QFP-80	PLASTIC, DIP-64	PLASTIC, DIP-64
Contacts	68	64	64	80	80	80	68	80	64	64
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	unknown	compliant	unknown	unknown	unknown
Other features	DYNAMIC REFRESH CONTROL; 1M BYTE PHYSICAL MEMORY	DYNAMIC REFRESH CONTROL; 1M BYTE PHYSICAL MEMORY	DYNAMIC REFRESH CONTROL; 1M BYTE PHYSICAL MEMORY	DYNAMIC REFRESH CONTROL; 1M BYTE PHYSICAL MEMORY	DYNAMIC REFRESH CONTROL; 1M BYTE PHYSICAL MEMORY	DYNAMIC REFRESH CONTROL; 1M BYTE PHYSICAL MEMORY	DYNAMIC REFRESH CONTROL; 1M BYTE PHYSICAL MEMORY	DYNAMIC REFRESH CONTROL; 1M BYTE PHYSICAL MEMORY	DYNAMIC REFRESH CONTROL; 1M BYTE PHYSICAL MEMORY	DYNAMIC REFRESH CONTROL; 1M BYTE PHYSICAL MEMORY
bit size	8	8	8	8	8	8	8	8	8	8
JESD-30 code	S-PQCC-J68	R-PDIP-T64	R-PDIP-T64	R-PQFP-G80	R-PQFP-G80	R-PQFP-G80	S-PQCC-J68	R-PQFP-G80	R-PDIP-T64	R-PDIP-T64
JESD-609 code	e3	e3	e3	e3	e3	e0	e3	e0	e0	e0
length	24.2316 mm	57.785 mm	57.785 mm	20 mm	20 mm	20 mm	24.2316 mm	20 mm	57.785 mm	57.785 mm
Number of terminals	68	64	64	80	80	80	68	80	64	64
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QCCJ	SDIP	SDIP	QFP	QFP	QFP	QCCJ	QFP	SDIP	SDIP
Package shape	SQUARE	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	SQUARE	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	CHIP CARRIER	IN-LINE, SHRINK PITCH	IN-LINE, SHRINK PITCH	FLATPACK	FLATPACK	FLATPACK	CHIP CARRIER	FLATPACK	IN-LINE, SHRINK PITCH	IN-LINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260	NOT SPECIFIED	NOT SPECIFIED	260	260	225	260	225	225	225
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	4.57 mm	5.01 mm	5.01 mm	3.1 mm	3.1 mm	3.1 mm	4.57 mm	3.1 mm	5.01 mm	5.01 mm
speed	8 MHz	6 MHz	8 MHz	6 MHz	8 MHz	6 MHz	6 MHz	8 MHz	8 MHz	6 MHz
Maximum slew rate	50 mA	40 mA	50 mA	40 mA	50 mA	40 mA	40 mA	50 mA	50 mA	40 mA
Maximum supply voltage	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	YES	NO	NO	YES	YES	YES	YES	YES	NO	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Matte Tin (Sn)	MATTE TIN	MATTE TIN	Matte Tin (Sn)	Matte Tin (Sn)	Tin/Lead (Sn/Pb)	MATTE TIN	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	J BEND	THROUGH-HOLE	THROUGH-HOLE	GULL WING	GULL WING	GULL WING	J BEND	GULL WING	THROUGH-HOLE	THROUGH-HOLE
Terminal pitch	1.27 mm	1.778 mm	1.778 mm	0.8 mm	0.8 mm	0.8 mm	1.27 mm	0.8 mm	1.78 mm	1.78 mm
Terminal location	QUAD	DUAL	DUAL	QUAD	QUAD	QUAD	QUAD	QUAD	DUAL	DUAL
Maximum time at peak reflow temperature	40	NOT SPECIFIED	NOT SPECIFIED	40	40	30	40	30	30	30
width	24.2316 mm	19.05 mm	19.05 mm	14 mm	14 mm	14 mm	24.2316 mm	14 mm	19.05 mm	19.05 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER	MICROCONTROLLER	MICROCONTROLLER	MICROCONTROLLER	MICROCONTROLLER	MICROPROCESSOR	MICROCONTROLLER	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR
Maker	IXYS	-	-	IXYS	IXYS	IXYS	IXYS	IXYS	IXYS	IXYS
Has ADC	NO	NO	NO	NO	NO	-	NO	-	-	-
Address bus width	20	18	18	19	19	-	19	-	-	-
boundary scan	NO	NO	NO	NO	NO	-	NO	-	-	-
maximum clock frequency	8 MHz	6 MHz	8 MHz	6 MHz	8 MHz	-	6 MHz	-	-	-
DAC channel	NO	NO	NO	NO	NO	-	NO	-	-	-
DMA channel	YES	YES	YES	YES	YES	-	YES	-	-	-
External data bus width	8	8	8	8	8	-	8	-	-	-
Format	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT	-	FIXED POINT	-	-	-
Integrated cache	NO	NO	NO	NO	NO	-	NO	-	-	-
low power mode	YES	YES	YES	YES	YES	-	YES	-	-	-
Number of DMA channels	2	2	2	2	2	-	2	-	-	-
Number of external interrupt devices	4	4	4	4	4	-	4	-	-	-
Number of serial I/Os	3	3	3	3	3	-	3	-	-	-
Number of timers	2	2	2	2	2	-	2	-	-	-
PWM channel	NO	NO	NO	NO	NO	-	NO	-	-	-

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