SPP100N08S2-07
SPB100N08S2-07
OptiMOS
®
Power-Transistor
Feature
•
N-Channel
Product Summary
V
DS
R
DS(on)
max. SMD version
I
D
P- TO263 -3-2
75
6.8
100
P- TO220 -3-1
V
mΩ
A
•
Enhancement mode
•
175°C operating temperature
•
Avalanche rated
•
dv/dt rated
Type
SPP100N08S2-07
SPB100N08S2-07
Package
P- TO220 -3-1
P- TO263 -3-2
Ordering Code
Q67060-S6044
Q67060-S6046
Marking
PN0807
PN0807
Maximum Ratings,
at
T
j
= 25 °C, unless otherwise specified
Parameter
Symbol
Continuous drain current
1)
T
C
=25°C
Value
100
100
Unit
A
I
D
Pulsed drain current
T
C
=25°C
I
D puls
E
AS
E
AR
dv/dt
V
GS
P
tot
T
j ,
T
stg
400
810
30
6
±20
300
-55... +175
55/175/56
kV/µs
V
W
°C
mJ
Avalanche energy, single pulse
I
D
=80 ,
V
DD
=25V,
R
GS
=25Ω
Repetitive avalanche energy, limited by
T
jmax
2)
Reverse diode dv/dt
I
S
=100A,
V
DS
=60V,
di/dt=200A/µs,
T
jmax
=175°C
Gate source voltage
Power dissipation
T
C
=25°C
Operating and storage temperature
IEC climatic category; DIN IEC 68-1
Page 1
2003-05-09
SPP100N08S2-07
SPB100N08S2-07
Thermal Characteristics
Parameter
Characteristics
Thermal resistance, junction - case
Thermal resistance, junction - ambient, leaded
SMD version, device on PCB:
@ min. footprint
@ 6 cm
2
cooling area
3)
Symbol
min.
R
thJC
R
thJA
R
thJA
-
-
-
-
Values
typ.
0.3
-
-
-
max.
0.5
62
62
40
Unit
K/W
Electrical Characteristics,
at
T
j
= 25 °C, unless otherwise specified
Parameter
Static Characteristics
Drain-source breakdown voltage
V
GS
=0V,
I
D
=1mA
Symbol
min.
V
(BR)DSS
V
GS(th)
I
DSS
-
-
I
GSS
R
DS(on)
-
-
-
75
2.1
Values
typ.
-
3
max.
-
4
Unit
V
Gate threshold voltage,
V
GS
=
V
DS
I
D
=250µA
Zero gate voltage drain current
V
DS
=75V,
V
GS
=0V,
T
j
=25°C
V
DS
=75V,
V
GS
=0V,
T
j
=125°C
µA
0.01
1
1
1
100
100
nA
mΩ
5.6
5.3
7.1
6.8
Gate-source leakage current
V
GS
=20V,
V
DS
=0V
Drain-source on-state resistance
V
GS
=10V,
I
D
=66A
V
GS
=10V,
I
D
=66A, SMD version
1Current limited by bondwire ; with an
R
thJC
= 0.5K/W the chip is able to carry
I
D
= 133A at 25°C, for detailed
information see app.-note ANPS071E available at
www.infineon.com/optimos
2Defined by design. Not subject to production test.
3Device on 40mm*40mm*1.5mm epoxy PCB FR4 with 6cm² (one layer, 70 µm thick) copper area for drain
connection. PCB is vertical without blown air.
Page 2
2003-05-09
SPP100N08S2-07
SPB100N08S2-07
Electrical Characteristics
Parameter
Dynamic Characteristics
Transconductance
Input capacitance
Output capacitance
Reverse transfer capacitance
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Gate Charge Characteristics
Gate to source charge
Gate to drain charge
Gate charge total
Gate plateau voltage
Q
gs
Q
gd
Q
g
V
DD
=60V,
I
D
=100A,
V
GS
=0 to 10V
V
DD
=60V,
I
D
=100A
Symbol
Conditions
min.
Values
typ.
112
4530
1080
450
25
36
68
36
max.
-
Unit
g
fs
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
V
DS
≥2*I
D
*R
DS(on)max
,
I
D
=100A
V
GS
=0V,
V
DS
=25V,
f=1MHz
56
-
-
-
-
-
-
-
S
6020 pF
1440
680
38
54
100
55
ns
V
DD
=40V,
V
GS
=10V,
I
D
=100A,
R
G
=2.2Ω
-
-
-
-
25
82
153
5.5
33
120
200
-
nC
V
(plateau)
V
DD
=60V,
I
D
=100A
V
Reverse Diode
Inverse diode continuous
forward current
Inv. diode direct current, pulsed
Inverse diode forward voltage
Reverse recovery time
Reverse recovery charge
I
SM
V
SD
t
rr
Q
rr
V
GS
=0V,
I
F
=80A
V
R
=40V,
I
F =
l
S
,
di
F
/dt=100A/µs
I
S
T
C
=25°C
-
-
-
-
-
-
-
0.9
90
290
100
400
1.3
110
360
A
V
ns
nC
Page 3
2003-05-09
SPP100N08S2-07
SPB100N08S2-07
5 Typ. output characteristic
I
D
=
f
(V
DS
);
T
j
=25°C
parameter:
t
p
= 80 µs
240
SPP100N08S2-07
6 Typ. drain-source on resistance
R
DS(on)
=
f
(I
D
)
parameter:
V
GS
24
SPP100N08S2-07
P
tot
= 300W
i
V
[V]
GS
a
b
A
200
180
160
4.8
5.0
5.3
5.5
5.8
6.0
6.3
6.5
10.0
Ω
20
e
f
g
h
c
d
e
R
DS(on)
18
16
14
12
10
8
6
i
I
D
140
120
100
80
60
40
20
0
0
1
2
3
4
c
a
e
g
h
f
g
h
i
f
d
4
V
GS
[V] =
2
b
e
5.8
f
6.0
g
6.3
h
i
6.5 10.0
V
0
6
0
20
40
60
80
100
120
A
160
V
DS
I
D
7 Typ. transfer characteristics
I
D
=
f
(
V
GS
);
V
DS
≥
2 x
I
D
x
R
DS(on)max
parameter:
t
p
= 80 µs
220
8 Typ. forward transconductance
g
fs
= f(I
D
);
T
j
=25°C
parameter:
g
fs
120
A
180
160
140
120
S
100
90
g
fs
V
V
GS
I
D
80
70
60
100
50
80
60
40
20
0
0
1
2
3
4
5
40
30
20
10
0
7
0
20
40
60
80
100
A
I
D
140
Page 5
2003-05-09
Embedded System
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