LDS9003 / 9001
High Power LED Temperature and PWM Controller
with LED-Sense
TM
In-Situ LED T
J
Sensing
FEATURES
High temperature LED current de-rating and
TM
thermal control using the LED-Sense
algorithm that directly monitors LED T
junction
No external thermal sensor is required
Up to three temperature sensing and control
channels on LDS9003 supports multi-point
thermal monitoring or multi-color LED
applications; LDS9001 is a single channel
Programmable Temp vs. PWM Duty Cycle
profiles
(3 for LDS9003; 1 for LDS9001)
Integrated PWM for dimming control of high
brightness (HB) LED Drivers in logarithmic
duty cycle steps from 0% to 100%
(~ 0.17 dB /
step)
PWM Dimming Control range of 256:1
2
I C compatible serial programming interface
Interfaces to available high side HB LED
drivers and low cost microcontrollers
LDS9003 is available in a small footprint
2
3 mm x 3 mm 16-pin TQFN
2
LDS9001 is in a 3 x 2 mm 8-pin DFN
The LDS9003/9001 utilizes the LED-Sense™
sensing and control algorithm that directly measures
the LED junction and controls the temperature by
closed loop adjustment of the LED Driver current via
PWM duty cycle corrections.
The control loop real-time adjusts the LED current via
PWM correction codes in user programmed Look up
Tables (LUTs) assigned to each sensing channel.
The user programs desired correction profiles for
every 5ºC increment from -35ºC to 120ºC. A single
sensing channel and correction LUT is available in
the LDS900, whereas three correction profiles are
available in LDS9003 to support multi-point
temperature sensing or multi-color LED applications.
Integrated PWM generators support dimming and
LED temperature vs. current compensation. The
2
PWM duty cycle is programmable via the I C serial
interface from 0% to 100%. User-programmed 8-bit
codes are converted to 12-bit logarithmic steps of ~
0.17 dB per step. The PWM frequency is ~280 Hz to
minimize noise generation.
The EN logic input functions as a chip enable. A logic
HIGH applied at the EN pin allows the LDS9003 /
2
LDS9001 to respond to I C communications. An
optional external serial interface address pin is
available for use in multi-target applications.
The device operates from 2.5 to 5.5V.
The LDS9001 is available in an 8-lead 3 x 2 mm
DFN package. The LDS9003 is in a 16-lead 3 x 3
2
mm TQFN package.
2
APPLICATIONS
HB LED General Illumination Lighting
RGB LED Projectors
Architectural LED Lighting
DESCRIPTION
The LDS9003 is a 3-channel and LDS9001 is a 1-
channel LED junction temperature monitor and
control device intended for use in high power LED
solid state lighting applications. It connects directly to
a LED anode and the PWM input of available high
power HB drivers to real-time adjust LED current to
2
meet maximum LED temperature. A two wire I C
interface allows communication to a local low cost
microcontroller or other remote host processor
device.
LDS9003 / 9001 can improve thermal management
of high power LED systems by controlling reliable
LED junction temperature levels to meet maximum
operating lifetimes. In addition, it can reduce cost by
allowing operation at optimal LED current/luminance
levels minimizing the number HB LED lamps per
fixture required to meet illumination targets.
© 2009 IXYS Corp.
Characteristics subject to change without notice
1
Doc. No. 9003/9001DS, Rev.N1.1
LDS9003 / 9001
ABSOLUTE MAXIMUM RATINGS
Parameter
V
IN
, IPWMX, TSENSEx
EN, SDAT, SCLK, SADD voltage
Storage Temperature Range
Junction Temperature Range
Soldering Temperature
HBM
ESD Protection Level
MM
Rating
6
V
IN
+ 0.7V
-65 to +160
-40 to +125
300
2
200
Unit
V
V
°C
°C
°C
kV
V
RECOMMENDED OPERATING CONDITIONS
Parameter
V
IN
IPWMx
Junction Temperature Range
Rating
2.5 to 5.5
1
-40 to +125
Unit
V
mA
°C
Typical application circuit with external components is shown on page 1.
ELECTRICAL OPERATING CHARACTERISTICS
(Over recommended operating conditions unless specified otherwise) Vin = 3.6V, Cin = 0.1 µF, EN = High, T
AMB
= 25°C
Name
IPWMx Channel DC Current Level
Quiescent Current
EN = V
IN
Shutdown Current
PWM Frequency
# of PWM duty cycle steps
Conditions
Standby (no I C clock)
V
EN
= 0V
Log Mode steps
2
Min
0.8
60
240
10
Minimum PWM On Time
PWM resolution
PWM Step Size
PWM Steps for current adjust
of
Temperature Compensation Adjust Steps
Input current
EN Pin
High
Logic Level
Low
Thermal Shutdown
Thermal Hysteresis
Wake-up/Shutdown Delay Time from EN
Raising/Falling Edge
Log Mode
Log Mode
1-x Scale Mode
2-x Scale Mode
Active mode, EN = V
IN
Active Mode or Normal
Standby Mode
Typ
1
100
0.5
285
256
13.7
12
0.17
Max
1.2
140
1
320
20
Units
mA
µA
µA
Hz
µs
bits
dB/step
PWM
0
Steps/5 C
0
C
µA
V
°C
ms
ms
-7
-14
5
-1
1.2
150
20
10
250
0
0
1
0.4
Soft ramp disabled
Soft ramp enabled
© 2009 IXYS Corp.
Characteristics subject to change without notice
3
Doc. No. 9003/9001_DS, Rev.N1.1
LDS9003 / 9001
I C CHARACTERISTICS
Over recommended operating conditions unless otherwise specified for 2.5
VIN
5.5V,
over full ambient temperature range -40 to +85ºC.
2
Symbol
f
SCL
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
t
F
t
SU:STO
t
BUF
t
AA
t
DH
Parameter
SCL Clock Frequency
Hold Time (repeated) START condition
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up Time for a repeated START condition
Data In Hold Time
Data In Set-up Time
Rise Time of both SDAT and SCLK signals
Fall Time of both SDAT and SCLK signals
Set-up Time for STOP condition
Bus Free Time between a STOP and START condition
SCLK Low to SDAT Data Out and ACK Out
Data Out Hold Time
Min
0
0.6
1.3
0.6
0.6
0
100
Max
400
0.9
300
300
0.6
1.3
0.9
300
Unit
kHz
µs
µs
µs
µs
ns
ns
ns
ns
µs
µs
µs
ns
Figure 1: I C Bus Timing Diagram
2
READ OPERATION:
Option 1:
Standard protocol sequential read:
S
Slave Address
R
A
Data 0
A
Data 1
A
Data 2
Reg. m+2
Data n
Reg. m+n,
A*
P
From: Reg. m
Reg. m+1
where Reg. m is the last addressed in the write operation register
Option 2:
Random access:
S
Slave Address
R
A
Data m
A*
P
From reg. m, where Reg. m is the last addressed in the write operation register
Option 3:
Random access with combined (extended) protocol:
S
Slave Address
W
A
Register Address m
A
Sr
Slave Address
R
A
Data m
A*
P
WRITE OPERATION:
Option 1:
Standard protocol sequencial write:
S
Slave Address
W
A
Register Address m
A
Data 0
A
Data 1
Reg. m+1
A
Data 2
Reg. m+2
Data k
Reg. m+k
A*
P
To: Reg. m
© 2009 IXYS Corp.
Characteristics subject to change without notice
4
Doc. No. 9003/9001_DS, Rev.N1.1
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