V59C1512(404/804/164)QD
HIGH PERFORMANCE 512 Mbit DDR2 SDRAM
4 BANKS X 32Mbit X 4 (404)
4 BANKS X 16Mbit X 8 (804)
4 BANKS X 8Mbit X 16 (164)
37
DDR2-533
Clock Cycle Time (t
CK3
)
Clock Cycle Time (t
CK4
)
Clock Cycle Time (t
CK5
)
Clock Cycle Time (t
CK6
)
Clock Cycle Time (t
CK7
)
System Frequency (f
CK max
)
5ns
3.75ns
-
-
-
266 MHz
3
DDR2-667
5ns
3.75ns
3ns
-
-
333 MHz
25A
DDR2-800
5ns
3.75ns
3ns
2.5ns
-
400 MHz
25
DDR2-800
5ns
3.75ns
2.5ns
2.5ns
-
400 MHz
19A
DDR2-1066
5ns
3.75ns
2.5ns
2.5ns
1.87ns
533 MHz
Features
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Description
The V59C1512(404/804/164)QD is a four bank DDR
DRAM organized as 4 banks x 32Mbit x 4 (404), 4 banks x
16Mbit x 8 (804), or 4 banks x 8Mbit x 16 (164). The
V59C1512(404/804/164)QD achieves high speed data
transfer rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the output
data to a system clock.
The chip is designed to comply with the following key
DDR2 SDRAM features:(1) posted CAS with additive la-
tency, (2) write latency = read latency -1, (3) On Die Ter-
mination.
All of the control, address, circuits are synchronized
with the positive edge of an externally supplied clock. I/O
s are synchronized with a pair of bidirectional strobes
(DQS, DQS) in a source synchronous fashion.
Operating the four memory banks in an interleaved
fashion allows random access operation to occur at a
higher rate than is possible with standard DRAMs. A se-
quential and gapless data rate is possible depending on
burst length, CAS latency and speed grade of the device.
Available Speed Grade:
-37 (DDR2-533) @ CL 4-4-4
-3 (DDR2-667) @ CL 5-5-5
-25A (DDR2-800) @ CL 6-6-6
-25 (DDR2-800) @ CL 5-5-5
-19A(DDR2-1066)@CL 7-7-7
High speed data transfer rates with system frequency
up to 533MHz
Posted CAS
Programmable CAS Latency: 3, 4, 5, 6 and 7
Programmable Additive Latency:0, 1, 2, 3, 4, 5 and 6
Write Latency = Read Latency -1
Programmable Wrap Sequence: Sequential
or Interleave
Programmable Burst Length: 4 and 8
Automatic and Controlled Precharge Command
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 7.8 us (8192 cycles/64 ms)
ODT (On-Die Termination)
Weak Strength Data-Output Driver Option
Bidirectional differential Data Strobe (Single-ended
data-strobe is an optional feature)
On-Chip DLL aligns DQ and DQs transitions with CK
transitions
Differential clock inputs CK and CK
JEDEC Power Supply 1.8V ± 0.1V
Available in 60-ball FBGA for x4 and x8 component or
84 ball FBGA for x16 component
All inputs & outputs are compatible with SSTL_18 in-
terface
tRAS lockout supported
Read Data Strobe supported (x8 only)
Internal four bank operations with single pulsed RAS
Device Usage Chart
Operating
Temperature
Range
0°C
≤
Tc
≤
85°C
-25°C
≤
Tc
≤
95°C
-40°C
≤
Tc
≤
95°C
Package Outline
60 ball FBGA
84 ball FBGA
•
•
•
CK Cycle Time (ns)
-37
•
•
•
Power
-19A
•
•
•
-3
•
•
•
-25A
•
•
•
-25
•
•
•
Std.
•
•
•
L
•
•
•
Temperature
Mark
Blank
M
I
V59C1512(404/804/164)QD Rev. 1.7 July 2011
1
FPGA/CPLD
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