®
X1226
4K (512 x 8), 2-Wire
™
RTC
Data Sheet
July 21, 2005
FN8098.1
Real Time Clock/Calendar with EEPROM
FEATURES
• Real Time Clock/Calendar
—Tracks time in Hours, Minutes, and Seconds
—Day of the Week, Day, Month, and Year
• 2 Polled Alarms (Non-volatile)
—Settable on the Second, Minute, Hour, Day of
the Week, Day, or Month
—Repeat Mode (periodic interrupts)
• Oscillator Compensation on chip
—Internal feedback resistor and compensation
capacitors
—64 position Digitally Controlled Trim Capacitor
—6 digital frequency adjustment settings to
±30ppm
• Battery Switch or Super Cap Input
• 512 x 8 Bits of EEPROM
—64-Byte Page Write Mode
—8 modes of Block Lock™ Protection
—Single Byte Write Capability
• High Reliability
—Data Retention: 100 years
—Endurance: 100,000 cycles per byte
• 2-Wire™ Interface interoperable with I2C
—400kHz data transfer rate
• Frequency Output (SW Selectable: Off, 1Hz,
4096Hz or 32.768kHz)
• Low Power CMOS
—1.25µA Operating Current (Typical)
• Small Package Options
—8-Lead SOIC and 8-Lead TSSOP
• Repetitive Alarms
• Temperature Compensation
• Pb-Free Plus Anneal Available (RoHS Compliant)
BLOCK DIAGRAM
OSC
Compensation
X1
Frequency
Divider
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Utility Meters
HVAC Equipment
Audio / Video Components
Set Top Box / Television
Modems
Network Routers, Hubs, Switches, Bridges
Cellular Infrastructure Equipment
Fixed Broadband Wireless Equipment
Pagers / PDA
POS Equipment
Test Meters / Fixtures
Office Automation (Copiers, Fax)
Home Appliances
Computer Products
Other Industrial / Medical / Automotive
DESCRIPTION
The X1226 device is a Real Time Clock with
clock/calendar, two polled alarms with integrated
512x8 EEPROM, oscillator compensation, and battery
backup switch.
The oscillator uses an external, low-cost 32.768kHz
crystal. All compensation and trim components are
integrated on the chip. This eliminates several external
discrete components and a trim capacitor, saving
board area and component cost.
32.768kHz
X2
Oscillator
1Hz
Timer
Calendar
Logic
Time
Keeping
Registers
(SRAM)
Battery
Switch
Circuitry
V
CC
V
BACK
PHZ/IRQ
Select
Status
Registers
(SRAM)
Mask
SCL
SDA
Serial
Interface
Decoder
Control
Decode
Logic
Control/
Registers
(EEPROM)
Alarm
Compare
Alarm Regs
(EEPROM)
4K
EEPROM
ARRAY
8
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X1226
PIN CONFIGURATION
8-Pin SOIC
X1
X2
PHZ/IRQ
V
SS
1
2
3
4
8
7
6
5
V
CC
V
BACK
SCL
SDA
V
BACK
V
CC
X1
X2
8-Pin TSSOP
1
2
3
4
8
7
6
5
SCL
SDA
V
SS
PHZ/IRQ
PIN ASSIGNMENTS
Pin Number
SOIC
1
TSSOP
3
Symbol
X1
Brief Description
X1.
The X1pin is the input of an inverting amplifier. An external 32.768kHz quartz
crystal is used with the X1226 to supply a timebase for the real time clock. The
recommended crystal is a Citizen CFS206-32.768KDZF. Internal compensation circuitry is
included to form a complete oscillator circuit. Care should be taken in the placement of the
crystal and the layout of the circuit. Plenty of ground plane around the device and short
traces to X1 are highly recommended. See Application section for more recommendations.
X2.
The X2 pin is the output of an inverting amplifier. An external 32.768kHz quartz
crystal is used with the X1226 to supply a timebase for the real time clock. The
recommended crystal is a Citizen CFS206-32.768KDZF. Internal compensation circuitry is
included to form a complete oscillator circuit. Care should be taken in the placement of the
crystal and the layout of the circuit. Plenty of ground plane around the device and short
traces to X2 are highly recommended. See Application section for more recommendations.
Programmable Frequency/Interrupt Output – PHZ/IRQ.
This is either an output from
the internal oscillator or an interrupt signal output. It is an open drain output.
When used as frequency output, this signal has a frequency of 32.768kHz, 4096Hz,
1Hz or inactive.
When used as interrupt output, this signal notifies a host processor that an alarm has
occurred and an action is required. It is an active LOW output.
The control bits for this function are FO1 and FO0 and are found in address 0011h of
the Clock Control Memory map. See “Programmable Frequency Output Bits—FO1,
FO0” on page 7.
V
SS
.
Serial Data (SDA).
SDA is a bidirectional pin used to transfer data into and out of the
device. It has an open drain output and may be wire ORed with other open drain or
open collector outputs. The input buffer is always active (not gated).
An open drain output requires the use of a pull-up resistor. The output circuitry controls
the fall time of the output signal with the use of a slope controlled pull-down. The circuit
is designed for 400kHz 2-wire interface speed.
Serial Clock (SCL).
The SCL input is used to clock all data into and out of the device.
The input buffer on this pin is always active (not gated).
V
BACK
.
This input provides a backup supply voltage to the device. V
BACK
supplies
power to the device in the event the V
CC
supply fails. This pin can be connected to a
battery, a Supercap or tied to ground if not used.
V
CC
.
2
4
X2
3
5
PHZ/IRQ
4
5
6
7
V
SS
SDA
6
7
8
1
SCL
V
BACK
8
2
V
CC
2
FN8098.1
July 21, 2005
X1226
DESCRIPTION
(continued)
The Real-Time Clock keeps track of time with
separate registers for Hours, Minutes, Seconds. The
Calendar has separate registers for Date, Month, Year
and Day-of-week. The calendar is correct through
2099, with automatic leap year correction.
The powerful Dual Alarms can be set to any
Clock/Calendar value for a match. For instance, every
minute, every Tuesday, or 5:23 AM on March 21. The
alarms can be polled in the Status Register or provide
a hardware interrupt (IRQ Pin). There is a repeat
mode for the alarms allowing a periodic interrupt.
The PHZ/IRQ pin may be software selected to provide
a frequency output of 1 Hz, 4096 Hz, or 32,768 Hz.
The device offers a backup power input pin. This
V
BACK
pin allows the device to be backed up by
battery or SuperCap. The entire X1226 device is fully
operational from 2.7 to 5.5 volts and the
clock/calendar portion of the X1226 device remains
fully operational down to 1.8 volts (Standby Mode).
The X1226 device provides 4K bits of EEPROM with 8
modes of BlockLock™ control. The BlockLock allows a
safe, secure memory for critical user and configuration
data, while allowing a large user storage area.
PIN DESCRIPTIONS
X1226
8-Pin SOIC
X1
X2
1
2
3
4
8
7
6
5
V
CC
V
BACK
SCL
SDA
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and
out of the device. It has an open drain output and may
be wire ORed with other open drain or open collector
outputs. The input buffer is always active (not gated).
An open drain output requires the use of a pull-up
resistor. The output circuitry controls the fall time of
the output signal with the use of a slope controlled
pull-down. The circuit is designed for 400kHz 2-wire
interface speed.
V
BACK
This input provides a backup supply voltage to the
device. V
BACK
supplies power to the device in the
event the V
CC
supply fails. This pin can be connected
to a battery, a Supercap or tied to ground if not used.
Programmable Frequency/Interrupt Output – PHZ/IRQ
This is either an output from the internal oscillator or an
interrupt signal output. It is an open drain output.
When used as frequency output, this signal has a
frequency of 32.768kHz, 4096Hz, 1Hz or inactive.
When used as interrupt output, this signal notifies a
host processor that an alarm has occurred and an
action is required. It is an active LOW output.
The control bits for this function are FO1 and FO0 and
are found in address 0011h of the Clock Control Mem-
ory map. See “Programmable Frequency Output
Bits—FO1, FO0” on page 7.
8-Pin TSSOP
V
BACK
V
CC
X1
X2
1
2
3
4
8
7
6
5
SCL
SDA
V
SS
PHZ/IRQ
X1, X2
The X1 and X2 pins are the input and output,
respectively, of an inverting amplifier. An external
32.768kHz quartz crystal is used with the X1226 to
supply a timebase for the real time clock. The
recommended crystal is a Citizen CFS206-32.768KDZF.
Internal compensation circuitry is included to form a
complete oscillator circuit. Care should be taken in the
placement of the crystal and the layout of the circuit.
Plenty of ground plane around the device and short
traces to X1 and X2 are highly recommended. See
Application section for more recommendations.
Figure 1. Recommended Crystal connection
X1
X2
PHZ/IRQ
V
SS
NC = No internal connection
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device. The input buffer on this pin is always active
(not gated).
3
FN8098.1
July 21, 2005
X1226
POWER CONTROL OPERATION
The power control circuit accepts a V
CC
and a V
BACK
input. The power control circuit powers the clock from
V
BACK
when V
CC
< V
BACK
– 0.2V. It will switch back to
power the device from V
CC
when V
CC
exceeds V
BACK
.
Figure 2. Power Control
V
CC
Voltage
the stop bit is written. The RTC continues to update
the time while an RTC register write is in progress and
the RTC continues to run during any nonvolatile write
sequences. A single byte may be written to the RTC
without affecting the other bytes.
Accuracy of the Real Time Clock
The accuracy of the Real Time Clock depends on the
frequency of the quartz crystal that is used as the time
base for the RTC. Since the resonant frequency of a
crystal is temperature dependent, the RTC perfor-
mance will also be dependent upon temperature. The
frequency deviation of the crystal is a fuction of the
turnover temperature of the crystal from the crystal’s
nominal frequency. For example, a >20ppm frequency
deviation translates into an accuracy of >1 minute per
month. These parameters are available from the crystal
manufacturer. Intersil’s RTC family provides on-chip
crystal compensation networks to adjust load-
capacitance to tune oscillator frequency from +116 ppm
to -37 ppm when using a 12.5 pF load crystal. For more
detail information see the Application section.
CLOCK/CONTROL REGISTERS (CCR)
The Control/Clock Registers are located in an area
separate from the EEPROM array and are only
accessible following a slave byte of “1101111x” and
reads or writes to addresses [0000h:003Fh]. The
clock/control memory map has memory addresses
from 0000h to 003Fh. The defined addresses are
described in the Table 1. Writing to and reading from
the undefined addresses are not recommended.
CCR Access
The contents of the CCR can be modified by perform-
ing a byte or a page write operation directly to any
address in the CCR. Prior to writing to the CCR
(except the status register), however, the WEL and
RWEL bits must be set using a two step process (See
section “Writing to the Clock/Control Registers.”)
The CCR is divided into 5 sections. These are:
1.
2.
3.
4.
5.
Alarm 0 (8 bytes; non-volatile)
Alarm 1 (8 bytes; non-volatile)
Control (4 bytes; non-volatile)
Real Time Clock (8 bytes; volatile)
Status (1 byte; volatile)
V
BACK
Off
On
In
REAL TIME CLOCK OPERATION
The Real Time Clock (RTC) uses an external
32.768kHz quartz crystal to maintain an accurate inter-
nal representation of the second, minute, hour, day,
date, month, and year. The RTC has leap-year correc-
tion. The clock also corrects for months having fewer
than 31 days and has a bit that controls 24 hour or
AM/PM format. When the X1226 powers up after the
loss of both V
CC
and V
BACK
, the clock will not operate
until at least one byte is written to the clock register.
Reading the Real Time Clock
The RTC is read by initiating a Read command and
specifying the address corresponding to the register of
the Real Time Clock. The RTC Registers can then be
read in a Sequential Read Mode. Since the clock runs
continuously and a read takes a finite amount of time,
there is the possibility that the clock could change during
the course of a read operation. In this device, the time is
latched by the read command (falling edge of the clock
on the ACK bit prior to RTC data output) into a separate
latch to avoid time changes during the read operation.
The clock continues to run. Alarms occurring during a
read are unaffected by the read operation.
Writing to the Real Time Clock
The time and date may be set by writing to the RTC
registers. To avoid changing the current time by an
uncompleted write operation, the current time value is
loaded into a separate buffer at the falling edge of the
clock on the ACK bit before the RTC data input bytes,
the clock continues to run. The new serial input data
replaces the values in the buffer. This new RTC value
is loaded back into the RTC Register by a stop bit at
the end of a valid write sequence. An invalid write
operation aborts the time update procedure and the
contents of the buffer are discarded. After a valid write
operation the RTC will reflect the newly loaded data
beginning with the next “one second” clock cycle after
4
Each register is read and written through buffers. The
non-volatile portion (or the counter portion of the RTC) is
updated only if RWEL is set and only after a valid write
operation and stop bit. A sequential read or page write
operation provides access to the contents of only one
section of the CCR per operation. Access to another sec-
tion requires a new operation. Continued reads or writes,
FN8098.1
July 21, 2005
X1226
once reaching the end of a section, will wrap around to
the start of the section. A read or write can begin at any
address in the CCR.
It is not necessary to set the RWEL bit prior to writing
the status register. Section 5 (status register) supports
a single byte read or write only. Continued reads or
writes from this section terminates the operation.
The state of the CCR can be read by performing a ran-
dom read at any address in the CCR at any time. This
returns the contents of that register location. Additional
Table 1. Clock/Control Memory Map
Addr.
Type
Reg
Name
Range
Default
Bit
7
6
5
4
3
2
1
0
(optional)
registers are read by performing a sequential read.
The read instruction latches all Clock registers into a
buffer, so an update of the clock does not change the
time being read. A sequential read of the CCR will not
result in the output of data from the memory array. At
the end of a read, the master supplies a stop condition
to end the operation and free the bus. After a read of
the CCR, the address remains at the previous address
+1 so the user can execute a current address read of
the CCR and continue reading the next Register.
003F
0037
0036
0035
0034
0033
0032
0031
0030
0013
0012
0011
0010
000F
000E
000D
000C
000B
000A
0009
0008
0007
0006
0005
0004
0003
0002
0001
0000
Status
RTC
(SRAM)
SR
Y2K
DW
YR
MO
DT
HR
MN
SC
BAT
0
0
Y23
0
0
MIL
0
0
0
0
IM
BP2
0
EDW1
EMO1
EDT1
EHR1
EMN1
ESC1
0
EDW0
EMO0
EDT0
EHR0
EMN0
ESC0
AL1
0
0
Y22
0
0
0
M22
S22
0
0
AL1E
BP1
0
0
0
0
0
A1M22
A1S22
0
0
0
0
0
A0M22
A0S22
AL0
Y2K21
0
Y21
0
D21
H21
M21
S21
0
ATR5
AL0E
BP0
A1Y2K21
0
0
A1D21
A1H21
A1M21
A1S21
A0Y2K21
0
0
A0D21
A0H21
A0M21
A0S21
0
Y2K20
0
Y20
G20
D20
H20
M20
S20
0
ATR4
FO1
0
A1Y2K20
0
A1G20
A1D20
A1H20
A1M20
A1S20
A0Y2K20
0
A0G20
A0D20
A0H20
A0M20
A0S20
0
Y2K13
0
Y13
G13
D13
H13
M13
S13
0
ATR3
FO0
0
A1Y2K13
0
A1G13
A1D13
A1H13
A1M13
A1S13
A0Y2K13
0
A0G13
A0D13
A0H13
A0M13
A0S13
RWEL
0
DY2
Y12
G12
D12
H12
M12
S12
DTR2
ATR2
X
0
0
DY2
A1G12
A1D12
A1H12
A1M12
A1S12
0
DY2
A0G12
A0D12
A0H12
A0M12
A0S12
WEL
0
DY1
Y11
G11
D11
H11
M11
S11
DTR1
ATR1
X
0
0
DY1
A1G11
A1D11
A1H11
A1M11
A1S11
0
DY1
A0G11
A0D11
A0H11
A0M11
A0S11
RTCF
Y2K10
DY0
Y10
G10
D10
H10
M10
S10
DTR0
ATR0
X
0
A1Y2K10
DY0
A1G10
A1D10
A1H10
A1M10
A1S10
A0Y2K10
DY0
A0G10
A0D10
A0H10
A0M10
A0S10
19/20
0-6
1-12
1-31
0-23
0-59
0-59
19/20
0-6
1-12
1-31
0-23
0-59
0-59
19/20
0-6
0-99
1-12
1-31
0-23
0-59
0-59
01h
20h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
20h
00h
00h
00h
00h
00h
00h
20h
00h
00h
00h
00h
00h
00h
Control
(EEPROM)
DTR
ATR
INT
BL
Alarm1
(EEPROM)
Y2K1
DWA1
YRA1
MOA1
DTA1
HRA1
MNA1
SCA1
Unused - Default = RTC Year value (No EEPROM) - Future expansion
Alarm0
(EEPROM)
Y2K0
DWA0
YRA0
MOA0
DTA0
HRA0
MNA0
SCA0
Unused - Default = RTC Year value (No EEPROM) - Future expansion
5
FN8098.1
July 21, 2005
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