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MT47H256M4HR-3EAT:E

Description
DDR DRAM, 256MX4, 0.4ns, CMOS, PBGA84, ROHS COMPLAINT, PLASTIC, FBGA-84
Categorystorage    storage   
File Size9MB,135 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Environmental Compliance  
Download Datasheet Parametric View All

MT47H256M4HR-3EAT:E Overview

DDR DRAM, 256MX4, 0.4ns, CMOS, PBGA84, ROHS COMPLAINT, PLASTIC, FBGA-84

MT47H256M4HR-3EAT:E Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerMicron Technology
Parts packaging codeBGA
package instructionTFBGA,
Contacts84
Reach Compliance Codecompliant
ECCN codeEAR99
access modeMULTI BANK PAGE BURST
Maximum access time0.4 ns
Other featuresAUTO/SELF REFRESH
JESD-30 codeR-PBGA-B84
JESD-609 codee1
length12.5 mm
memory density1073741824 bit
Memory IC TypeDDR DRAM
memory width4
Number of functions1
Number of ports1
Number of terminals84
word count268435456 words
character code256000000
Operating modeSYNCHRONOUS
Maximum operating temperature105 °C
Minimum operating temperature-40 °C
organize256MX4
Package body materialPLASTIC/EPOXY
encapsulated codeTFBGA
Package shapeRECTANGULAR
Package formGRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum seat height1.2 mm
self refreshYES
Maximum supply voltage (Vsup)1.9 V
Minimum supply voltage (Vsup)1.7 V
Nominal supply voltage (Vsup)1.8 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Silver/Copper (Sn/Ag/Cu)
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature30
width8 mm
Base Number Matches1
1Gb: x4, x8, x16 DDR2 SDRAM
Features
DDR2 SDRAM
MT47H256M4 – 32 Meg x 4 x 8 banks
MT47H128M8 – 16 Meg x 8 x 8 banks
MT47H64M16 – 8 Meg x 16 x 8 banks
Features
Vdd = +1.8V ±0.1V, VddQ = +1.8V ±0.1V
JEDEC-standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
4n-bit prefetch architecture
Duplicate output strobe (RDQS) option for x8
DLL to align DQ and DQS transitions with CK
8 internal banks for concurrent operation
Programmable CAS latency (CL)
Posted CAS additive latency (AL)
WRITE latency = READ latency - 1
t
CK
Selectable burst lengths (BL): 4 or 8
Adjustable data-output drive strength
64ms, 8,192-cycle refresh
On-die termination (ODT)
Industrial temperature (IT) option
RoHS compliant
Supports JEDEC clock jitter specification
Options
1
Configuration
256 Meg x 4 (32 Meg x 4 x 8 banks)
128 Meg x 8 (16 Meg x 8 x 8 banks)
64 Meg x 16 (8 Meg x 16 x 8 banks)
FBGA package (Pb-free) – x16
84-ball FBGA (8mm x 12.5mm) Rev. E, G
FBGA package (Pb-free) – x4, x8
60-ball FBGA (8mm x 11.5mm) Rev. E, G
FBGA package (lead solder) – x16
84-ball FBGA (8mm x 12.5mm) Rev. E, G
FBGA package (lead solder) – x4, x8
60-ball FBGA (8mm x 11.5mm) Rev. E, G
Timing – cycle time
1.875ns @ CL = 7 (DDR2-1066)
2.5ns @ CL = 5 (DDR2-800)
2.5ns @ CL = 6 (DDR2-800)
3.0ns @ CL = 4 (DDR2-667)
3.0ns @ CL = 5 (DDR2-667)
3.75ns @ CL = 4 (DDR2-533)
Self refresh
Standard
Low-power
Operating temperature
Commercial (0°C
T
C
85°C)
Industrial (–40°C
T
C
95°C;
–40°C
T
A
85°C)
Automotive (–40°C
T
C
, T
A
105ºC)
Revision
Note:
Marking
256M4
128M8
64M16
HR
HQ
HW
HV
-187E
-25E
-25
-3E
-3
-37E
None
L
None
IT
AT
:E/:G
1. Not all options listed can be combined to
define an offered product. Use the Part
Catalog Search on
www.micron.com
for
product offerings and availability.
PDF: 09005aef821ae8bf
Rev. P 1/09 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2004 Micron Technology, Inc. All rights reserved.
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