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EDS2508AFTA-7A-E

Description
Synchronous DRAM, 32MX8, 5.4ns, CMOS, PDSO54, ROHS COMPLIANT, PLASTIC, TSOP2-54
Categorystorage    storage   
File Size734KB,50 Pages
ManufacturerELPIDA
Websitehttp://www.elpida.com/en
Environmental Compliance
Download Datasheet Parametric View All

EDS2508AFTA-7A-E Overview

Synchronous DRAM, 32MX8, 5.4ns, CMOS, PDSO54, ROHS COMPLIANT, PLASTIC, TSOP2-54

EDS2508AFTA-7A-E Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerELPIDA
Parts packaging codeTSOP2
package instructionTSOP2, TSOP54,.46,32
Contacts54
Reach Compliance Codeunknown
ECCN codeEAR99
access modeFOUR BANK PAGE BURST
Maximum access time5.4 ns
Other featuresAUTO/SELF REFRESH
Maximum clock frequency (fCLK)133 MHz
I/O typeCOMMON
interleaved burst length1,2,4,8
JESD-30 codeR-PDSO-G54
JESD-609 codee6
length22.22 mm
memory density268435456 bit
Memory IC TypeSYNCHRONOUS DRAM
memory width8
Number of functions1
Number of ports1
Number of terminals54
word count33554432 words
character code32000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize32MX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP2
Encapsulate equivalent codeTSOP54,.46,32
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply3.3 V
Certification statusNot Qualified
refresh cycle8192
Maximum seat height1.2 mm
self refreshYES
Continuous burst length1,2,4,8,FP
Maximum standby current0.002 A
Maximum slew rate0.2 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formGULL WING
Terminal pitch0.8 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width10.16 mm
Base Number Matches1
DATA SHEET
256M bits SDRAM
EDS2508AFTA-7A (32M words
×
8 bits)
Specifications
Density: 256M bits
Organization
8M words
×
8 bits
×
4 banks
Package: 54-pin plastic TSOP (II)
Lead-free (RoHS compliant)
Power supply: VDD, VDDQ
=
3.3V
±
0.3V
Clock frequency: 133MHz (max.)
Four internal banks for concurrent operation
Interface: LVTTL
Burst lengths (BL): 1, 2, 4, 8, full page
Burst type (BT):
Sequential (1, 2, 4, 8, full page)
Interleave (1, 2, 4, 8)
/CAS Latency (CL): 2, 3
Precharge: auto precharge option for each burst
access
Refresh: auto-refresh, self-refresh
Refresh cycles: 8192 cycles/64ms
Average refresh period: 7.8µs
Operating ambient temperature range
TA = 0°C to +70°C
Pin Configurations
/xxx indicate active low signal.
54-pin Plastic TSOP (II)
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
VDD
NC
/WE
/CAS
/RAS
/CS
BA0
BA1
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ7
VSSQ
EO
Features
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
VSS
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
Single pulsed /RAS
Burst read/write operation and burst read/single write
operation capability
Byte control by DQM
Document No. E1141E10 (Ver. 1.0)
Date Published July 2007 (K) Japan
Printed in Japan
URL: http://www.elpida.com
L
This product became EOL in April, 2010.
Elpida
Memory, Inc. 2007
od
Pr
A0 to A12
BA0, BA1
/CS
/RAS
/CAS
/WE
DQM
DQ0 to DQ7
(Top view)
Address input
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
CKE
CLK
VDD
VSS
Write enable
Input/output mask
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
uc
Power for DQ circuit
Ground for DQ circuit
No connection
VDDQ
VSSQ
NC
t
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