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TRU050THCGA12

Description
Phase Locked Loop, CDIP16, ROHS COMPLIANT, HERMETIC SEALED, CERAMIC, DIP-16
CategoryAnalog mixed-signal IC    The signal circuit   
File Size173KB,14 Pages
ManufacturerVectron International, Inc.
Websitehttp://www.vectron.com/
Environmental Compliance  
Download Datasheet Parametric View All

TRU050THCGA12 Overview

Phase Locked Loop, CDIP16, ROHS COMPLIANT, HERMETIC SEALED, CERAMIC, DIP-16

TRU050THCGA12 Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerVectron International, Inc.
Parts packaging codeDIP
package instructionROHS COMPLIANT, HERMETIC SEALED, CERAMIC, DIP-16
Contacts16
Reach Compliance Codecompliant
Analog Integrated Circuits - Other TypesPHASE LOCKED LOOP
JESD-30 codeR-CDIP-T16
JESD-609 codee4
length20.32 mm
Humidity sensitivity level1
Number of functions1
Number of terminals16
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum seat height4.69 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
Temperature levelCOMMERCIAL
Terminal surfaceGOLD OVER NICKEL
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperature40
width7.62 mm
Base Number Matches1
TRU050
Complete VCXO based Phase-Locked Loop
Features
Output Frequencies to 65.536 MHz
5.0 V or 3.3Vdc Operation
Tri-State Output
Holdover on Loss of Signal Alarm
VCXO with CMOS Outputs
0/70° or –40/85°C Temperature Range
Ceramic SMD Package
RoHS/Lead Free Compliant
The TRU050, VCXO based PLL
Description
The VI TRU050 is a user-configurable crystal-
based PLL integrated circuit. It includes a digital
phase detector, op-amp, VCXO and additional
integrated functions for use in digital
synchronization applications. Loop filter software
is available as well SPICE models for circuit
simulation.
Applications
Frequency Translation
Clock Smoothing
NRZ Clock Recovery
DSLAM, ADM, ATM, Aggregation, Optical
Switching/Routing, Base Station
Low Jitter PLL’s
Figure 1. TRU050 Block Diagram
Vectron International, 267 Lowell Rd, Hudson NH 03051-4916
Page 1 of 14
Tel: 1-88-VECTRON-1
Web:
www.vectron.com
Rev : 06Jan2006
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