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Teledyne DALSA
IL-P3-B Image
Sensors
Fast and sensitive, the IL-P3-B has been designed and
fabricated using the industry’s most sophisticated technology.
The IL-P3-B delivers consistently high image quality, and its
single output design reduces the cost and complexity of
support electronics.
Features
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Description
Physical Characteristics
Pixel dimensions
Active area 14µm x
Active pixels per line
Isolation pixels per line
Shielded pixels per line
IL-P3-B
14 µm x 14 µm
7.2 / 14.4 / 28.7 mm
512 / 1024 / 2048
20
6
Single output, 40 MHz data rate
Surface gated photodiodes for low lag
Line rate to 73 kHz (512 model)
Low voltage clocks (<5V)
14 µm (H) x 14 µm (V) pixels, 100% fill factor
512, 1024, or 2048 pixels
Antiblooming and exposure control
Highly sensitive, with responsivity reaching 43 V/(µJ/cm
2
)
RoHS compliant
Table 1. IL-P3-B Pin Functional Description
Pin
1
2
3
4, 11
5
6, 20
7, 10, 14
8
9
12
13
15, 16
17, 18
19
21
22
23
24
Symbol
VSS
OS
VDD
TCK
PR
VLS
NC
VPR
VSTOR
VLOW
VHIGH
CR2
CR1
VBB
CRLAST
VSET
RST
VOD
Name
Amplifier Return
Output Signal
Amplifier Supply
Transfer Gate
Pixel Reset Gate
Light Shield
No Connection
Pixel Reset Drain, Guard Ring
Pixel Storage Gate
Low Bias Voltage
High Bias Voltage
Readout Register, Phase 2
Readout Register, Phase 1
Substrate
Last Register
Output Node Set Gate
Output Reset Gate
Output Reset Drain
VSS 1
OS 2
VDD 3
TCK 4
PR 5
VLS 6
NC 7
VPR 8
VSTOR 9
NC 10
TCK 11
VLOW 12
24
23
22
21
20
19
18
17
16
15
14
13
VOD
RST
VSET
CRLAST
VLS
VBB
CR1
CR1
CR2
CR2
NC
VHIGH
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Teledyne DALSA INC.: Phone: 519-886-6000 Fax: 519-886-8023
Document number 03-036-00187-09
1
ISO 9001
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Figure 1. IL-P3-B Block Diagram
1
1
Relative position of package Pin 1
Table 2. # of Clock Drivers Required
Clock Drivers
Type
Speed
Low Voltage
High
Low Voltage
Low
Glitch
High
1.
2.
Min. # Required
PR
2
off
PR on
2
2
1
2
1
1
1
Table 3. # of DC Biases Required
DC Biases
Regulated?
Yes
No
1.
2.
# Required
1
PR
2
off
PR on
7
7
1
1
Redundant clock drivers may be required to drive the
CCD input capacitance. Refer to Figure 7 for details.
PR = Pixel Reset (exposure control).
Refer to Figure 7 for details.
PR = Pixel Reset (exposure control).
The IL-P3-B series of linear CCD image sensors use proprietary
technology to provide a single output at 40 MHz. The series
employs buried channel CCD shift registers to maximize output
speed and reduce noise. The sensor has a dynamic range of
>1800:1 and provides output which is linear for the operating
range of light input. The IL-P3-B’s exposure control allows
integration times shorter than the readout time. Proprietary
image sensor architecture provides low image lag pixels and
high blue response.
The IL-P3-B sensor’s superior performance makes it ideally
suited for applications requiring maximum speed and high
resolution, such as:
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The IL-P3-B series includes sensors with 512, 1024, or 2048
pixels with active imaging area lengths of 7, 14, and 28 mm,
respectively. Photoelements are 14 µm square for a
photosensitive area of 196 µm
2
and a 1:1 aspect ratio. Light
incident on these photoelements is converted into charge
packets whose size (i.e., number of electrons) is linearly
dependent on the light intensity and the integration time. The
charge is collected into a separate storage well (VSTOR)
adjacent to each photoelement. This helps to minimize image
lag, nonuniformities associated with the use of pixel reset, and
crosstalk between the photodiode and the CCD shift register.
With exposure control disabled, the integration time is the period
between successive pulses of the transfer (TCK) clock. The
integration time can be further reduced with electronic exposure
control using the pixel reset (PR) clock. The pixel reset clock
resets not the photoelements themselves but the storage well
adjacent to each photoelement. When PR is clocked, the
integration time becomes the duration between the falling edge
of the PR clock and the rising edge of the TCK clock.
When PR is clocked, the PR pulse must be damped to produce a
smooth PR pulse. If PR switches too rapidly, the uniformity of
Detection
High performance document scanning
Inspection
Optical character recognition
Functional Description
The IL-P3-B sensor is composed of three main functional
groups: surface gated photodiodes in which the signal charge
packets are generated, a single CCD readout shift registers, and
an output amplifier where the charge packets are converted to
voltage pulses.
2
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Teledyne DALSA INC.: Phone: 519-886-6000 Fax: 519-886-8023
Document number 03-036-00187-09
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For product information and updates visit www.teledynedalsa.com
the OS signal will be affected by the PR clock feedthrough. A
current-drive PR clock circuit generally introduces less
feedthrough than a voltage-drive circuit.
Antiblooming is always present when biases fall within the
specified operating conditions. By adjusting VSTOR however,
the user has the added flexibility of selecting the antiblooming
level (the signal level beyond which the additional signal charge
is drained away). A higher VSTOR bias results in a higher anti-
blooming level.
gate isolates the sense node diffusion from the last readout gate
and the rest of the readout shift register. As signal charges
accumulate on the floating node diffusion, the potential of this
diffusion decreases. The floating node diffusion is connected to
the input of a 2.5-stage low-noise amplifier, producing an output
signal voltage on the amplifier output (OS). The floating diffusion
is cleared of signal charge by the reset gate (RST) in preparation
for the next signal charge packet. The voltage level of the floating
diffusion after each reset is determined by the output reset drain
voltage (VOD). AC coupling the output is recommended to
eliminate the DC offset.
The output signal (OS) requires an off-chip load drawing
approximately 10mA of load current. If the load capacitance
(C
LOAD
) is greater than 10pF, larger load current (up to the 18mA
operating limit) may be required. As the load current increases,
the amplifier bandwidth increases. The amplifier can also drive
larger capacitive loads when the load current is larger. We
recommend however that just enough bandwidth be used since
larger bandwidth also results in increased noise.
If an off-chip current load is not available, the amplifier output
(OS) can be connected to a 1kW load resistor. The use of a
passive (resistive) load reduces the amplifier gain, resulting in
lower responsivity and saturation output signal. We do not
recommend passive loads at data rates greater than 25 MHz
because variations in DC offset will result in variations in
bandwidth.
The isolation pixels should not be used for calibration or
detection.
Transfer
The TCK clock controls the transfer of electrons from the
storage well into the 2-phase buried-channel CCD readout
register. Transfer is from the storage wells into the CR1 phases
of the readout register. The readout register is then used to
serially shift the charge packets to the high-speed low-noise
output amplifier.
The final phase of the readout register is connected separately to
CRLAST. This provides the flexibility of timing the transfer of
signal charges to the output node. CRLAST is normally clocked
in phase with CR1, but may be delayed (see Figure 4) to shift the
sampled portion of the output video away from clock
feedthroughs.
All CR clocks operate with 50% duty cycle.
Additional details on driving the sensor are provided on Figure 7.
Output
The signal charge packets from the readout shift register are
transferred serially from the last readout gate (CRLAST), over
the set gate (VSET), to a floating sense node diffusion. The set
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Teledyne DALSA INC.: Phone: 519-886-6000 Fax: 519-886-8023
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Table 4. IL-P3-B Absolute Maximum Ratings
Parameter
Storage Temp
Operating Temp
Voltage on CR1, CR2, VSTOR, TCK, PR, VLS
1
with
respect to VBB
Voltage on OS, VDD, VOD, VSS, VPR, VHIGH, CRLAST,
RST, VSET, VLOW with respect to VBB
Voltage on OSn with respect to VSS
Amplifier Load Current (I
LOAD
)
Unit
°C
°C
V
V
V
mA per output
Min.
-20
-20
-10
0
VDD-8
Max.
80
60
18
18
VDD+1
20
WARNING:
Exceeding these values will void product warranty and may damage the device.
Note:
1. When VOD or VDD is biased, ensure that VLS never deviates from VBB.
CAUTION! These devices are sensitive to damage from electrostatic
discharge (ESD). The leads should be shorted together during storage or
handling to prevent damage to the device.
WARNING: To prevent damage to the sensor, a Schottky diode must connect
VBB and VSS. See Figure 7.
Table 5. IL-P3-B Input/Output Characteristics
Input Characteristics:
Capacitance to VBB
1
from CR1, CR2
from CRLAST
from RST
from PR
from TCK
Output Characteristics:
2
Unit
512
pF
pF
pF
pF
pF
W
mA
V
70
9
7
31
20
Typical
1024
125
9
7
53
36
130W with I
LOAD
= 10 mA
14mA with I
LOAD
= 10 mA
8.3V with I
LOAD
= 10 mA
2048
250
9
7
99
70
Output Impedance (R
OUT
)
3
Amplifier Supply Current (I
DD
)
4
DC Output Offset (VOS)
5
Notes:
1. Using 1V pk-pk 1MHz signal with +5V DC offset.
2. The two CR1 pins (pins 17 and 18) are internally connected, as are the two CR2 pins (pins 15 and 16).
3. In general, R
OUT
(W)
~ 324 * (I
LOAD
)
-0.389
, I
LOAD
in mA.
4. In general, I
DD
(mA) = 4 + I
LOAD
, I
LOAD
in mA.
5. In general, V
OFFSET
(V) = 0.0018 * (I
LOAD
)
2
- 0.17 * (I
LOAD
) + 9.8, I
LOAD
in mA.
4
ISO 9001
Teledyne DALSA Corp.: Phone: 519-886-6000 Fax: 519-886-8023
Document number 03-036-00187-09
www.teledynedalsa.com
For product information and updates visit www.teledynedalsa.com
Table 6. IL-P3-B DC Operating Conditions
Symbol
I
LOAD
VDD
VOD
VSET
VSTOR
2, 4
VPR
VHIGH
VLOW
VBB
3
VLS
VSS
3
Description
Load current to the output (OS)
Amplifier supply
Output reset drain
Output node set gate
Pixel storage gate
Pixel reset drain, guard ring
High bias voltage
Low bias voltage
Substrate
Light shield
Amplifier return
Unit
mA
V
V
V
V
V
V
V
V
V
V
Min.
7.5
13.5
12.0
0.7
1.6
13
13
-0.5
-2.5
Rec.
1
10.0
14.0
12.5
1.2
2.0
14
14
0
-2
VBB
0
Max.
18.0
15.0
13.0
1.4
2.2
15
15
15
-1.5
Notes:
1. When deviating from the recommended biases, ensure that the new biases still meet the essential conditions on Table 8.
2. VSTOR may be adjusted to affect the antiblooming level. V
SAT
decreases by ~ 870mV for every 1.0V reduction in VSTOR.
3. VBB should never be forward biased with respect to VSS. To protect against damage, a Schottky diode between VBB and
VSS is recommended (see Figure 7).
4. The VSTOR operating limits are only valid for PR Low = 0V. When negative PR Low is applied, the VSTOR operating limits
should be read as the difference, (VSTOR - PR Low). The antiblooming is determined by this difference.
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Teledyne DALSA INC.: Phone: 519-886-6000 Fax: 519-886-8023
Document number 03-036-00187-09
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ISO 9001
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