K4S28323LE-HN1H0 datasheet, PDF

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K4S28323LE-HN1H0: DescriptionSynchronous DRAM, 4MX32, 7ns, CMOS, PBGA90, 9 X 13 MM, LEAD FREE, FBGA-90; Categorystorage storage; File Size77KB，10 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

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K4S28323LE-HN1H0 Overview

Synchronous DRAM, 4MX32, 7ns, CMOS, PBGA90, 9 X 13 MM, LEAD FREE, FBGA-90

K4S28323LE-HN1H0 Parametric

Parameter Name	Attribute value
Maker	SAMSUNG
Parts packaging code	BGA
package instruction	TFBGA,
Contacts	90
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	7 ns
Other features	AUTO/SELF REFRESH
JESD-30 code	R-PBGA-B90
length	13 mm
memory density	134217728 bit
Memory IC Type	SYNCHRONOUS DRAM
memory width	32
Number of functions	1
Number of ports	1
Number of terminals	90
word count	4194304 words
character code	4000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-25 °C
organize	4MX32
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Certification status	Not Qualified
Maximum seat height	1.2 mm
self refresh	YES
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
width	9 mm
Base Number Matches	1

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K4S28323LE-F(H)E/N/S/C/L/R

1M x 32Bit x 4 Banks SDRAM in 90FBGA

FEATURES

•

2.5V power supply

LVCMOS compatible with multiplexed address

Four banks operation

MRS cycle with address key programs

- CAS latency (1, 2 & 3)

- Burst length (1, 2, 4, 8 & Full page)

- Burst type (Sequential & Interleave)

Special Function Support

- Internal TCSR(Temperature Compensated Self Refresh)

- PASR(Partial Array Self Refresh)

All inputs are sampled at the positive going edge of the system

clock

Burst read single-bit write operation

DQM for masking.

Auto & self refresh

64ms refresh period (4K cycle).

Extended Temperature Operation (-25

°C

~ 85°C).

Commercial Temperature Operation (-25

°C

~ 70

°C).

90Balls Monolithic FBGA(9mm x 13mm)

Pb for -FXXX, Pb Free for -HXXX.

Mobile-SDRAM

GENERAL DESCRIPTION

The K4S28323LE is 134,217,728 bits synchronous high data

rate Dynamic RAM organized as 4 x 1,048,576 words by 32

bits, fabricated with SAMSUNG′s high performance CMOS

technology. Synchronous design allows precise cycle control

with the use of system clock and I/O transactions are possible

on every clock cycle. Range of operating frequencies, program-

mable burst lengths and programmable latencies allow the

same device to be useful for a variety of high bandwidth and

high performance memory system applications.

•

ORDERING INFORMATION

Part No.

Max Freq.

Interface Package

K4S28323LE-F(H)E/N/S/C/L/R60 166MHz(CL=3)

133MHz(CL=3)

90FBGA

105MHz(CL=2) LVCMOS

K4S28323LE-F(H)E/N/S/C/L/R1H 105MHz(CL=2)

(Pb Free)

K4S28323LE-F(H)E/N/S/C/L/R75

K4S28323LE-F(H)E/N/S/C/L/R1L 105MHz(CL=3)

- F(H)E/N/S : Normal/Low/Super Low Power, Extended Temp.

- F(H)C/L/R : Normal/Low/Super Low Power, Commercial Temp.

Note :

1. In case of 40MHz Frequency, CL1 can be supported.

FUNCTIONAL BLOCK DIAGRAM

I/O Control

LWE

Data Input Register

LDQM

Bank Select

1M x 32

Refresh Counter

Output Buffer

Row Decoder

Sense AMP

Row Buffer

DQi

Address Register

CLK

ADD

Column Decoder

Col. Buffer

LRAS

LCBR

Latency & Burst Length

LCKE

LRAS

LCBR

LWE

LCAS

Programming Register

LWCBR

LDQM

Timing Register

CLK

CKE

RAS

CAS

DQM

* Samsung Electronics reserves the right to change products or specification without notice.

May. 2003

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