IBM13N8734HC-365T datasheet, PDF

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IBM13N8734HC-365T: DescriptionSynchronous DRAM Module, 8MX72, 6.5ns, CMOS, DIMM-168; Categorystorage storage; File Size345KB，18 Pages; ManufacturerIBM; Websitehttp://www.ibm.com

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IBM13N8734HC-365T Overview

Synchronous DRAM Module, 8MX72, 6.5ns, CMOS, DIMM-168

IBM13N8734HC-365T Parametric

Parameter Name	Attribute value
Maker	IBM
Parts packaging code	DIMM
package instruction	DIMM, DIMM168
Contacts	168
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	6.5 ns
Maximum clock frequency (fCLK)	100 MHz
I/O type	COMMON
JESD-30 code	R-XDMA-N168
memory density	603979776 bit
Memory IC Type	SYNCHRONOUS DRAM MODULE
memory width	72
Number of functions	1
Number of ports	1
Number of terminals	168
word count	8388608 words
character code	8000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	8MX72
Output characteristics	3-STATE
Package body material	UNSPECIFIED
encapsulated code	DIMM
Encapsulate equivalent code	DIMM168
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
power supply	3.3 V
Certification status	Not Qualified
refresh cycle	4096
Maximum standby current	0.018 A
Maximum slew rate	1.395 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	NO LEAD
Terminal pitch	1.27 mm
Terminal location	DUAL
Base Number Matches	1

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IBM11M4730C4M x 72 E12/10, 5.0V, Au.

Preliminary

Features

IBM13N8644HC

IBM13N8734HC

8M x 64/72 1 Bank Unbuffered SDRAM Module

• 168-Pin Unbuffered 8-Byte Dual In-Line Memory

Module

• 8Mx64/72 Synchronous DRAM DIMM

• Four speed sorts:

• -360, -365, -370 for PC100 applications

• -10 for 66MHz applications (typical)

• Inputs and outputs are LVTTL (3.3V) compatible

• Single 3.3V

0.3V Power Supply

• Single Pulsed RAS interface

• SDRAMs have 4 internal banks

• Module has 1 bank

• Fully Synchronous to positive Clock Edge

• Data Mask for Byte Read/Write control

• Auto Refresh (CBR) and Self Refresh

• Automatic and controlled Precharge commands

• Programmable Operation:

- CAS Latency: 2, 3

- Burst Type: Sequential or Interleave

- Burst Length: 1, 2, 4, 8, Full-Page (Full-

Page supports Sequential burst only)

- Operation: Burst Read and Write or Multiple

Burst Read with Single Write

• Suspend Mode and Power Down Mode

• 12/9/2 Addressing (Row/Column/Bank)

• 4096 Refresh cycles distributed across 64ms

• Serial Presence Detect

• Card size: 5.25" x 1.375" x 0.167"

• Gold contacts

• SDRAMs in TSOP Type II Package

Description

IBM13N8644HC / IBM13N8734HC are unbuffered

168-pin Synchronous DRAM Dual In-Line Memory

Modules (DIMMs) which are organized as 8Mx64

and 8Mx72 high-speed memory arrays. The DIMMs

use 8 (8Mx64) or 9 (8Mx72) 8Mx8 SDRAMs in

400mil TSOP II packages. The DIMMs achieve

high-speed data transfer rates of up to 100MHz by

employing a prefetch/pipeline hybrid architecture

that supports the JEDEC 1N rule while allowing very

low burst power.

The -10 speed sort DIMMs comply with JEDEC

standards for 168-pin unbuffered SDRAM DIMMs.

The -360 speed sort DIMMs are compatible with the

Intel PC SDRAM unbuffered DIMM specification.

The -365 and -370 speed sorts are similar to the

-360 speed sort except that they have slower clock

access time (t

AC3

) and are targeted for more lightly

loaded PC100 applications.

All control, address, and data input/output circuits

are synchronized with the positive edge of the exter-

nally supplied clock inputs.

All inputs are sampled at the positive edge of each

externally supplied clock (CK0, CK2). Internal oper-

ating modes are defined by combinations of RAS,

CAS, WE, S0/S2, DQMB, and CKE0 signals. A

command decoder initiates the necessary timings

for each operation. A 14-bit address bus accepts

address information in a row/column multiplexing

arrangement.

Prior to any Access operation, the CAS latency,

burst type, burst length, and Burst operation type

must be programmed into the DIMM by address

inputs A0-A9 during the Mode Register Set cycle.

The DIMM uses serial presence detects imple-

mented via a serial EEPROM using the two-pin IIC

protocol. The first 128 bytes of serial PD data are

used by the DIMM manufacturer. The last 128 bytes

are available to the customer.

All IBM 168-pin DIMMs provide a high-performance,

flexible 8-byte interface in a 5.25" long space-saving

footprint. Related products include both EDO DRAM

and SDRAM unbuffered DIMMs in both non-parity

x64 and ECC-Optimized x72 configurations.

Card Outline

(Front) 1

(Back) 85

08J0430.E24453

Released 4/98

10 11

94 95

40 41

124 125

168

Use is further subject to the provisions at the end of this document.

Page 1 of 18

IBM13N8734HC-365T Related Products

	IBM13N8734HC-365T	IBM13N8644HC-370T	IBM13N8644HC-365T	IBM13N8734HC-370T
Description	Synchronous DRAM Module, 8MX72, 6.5ns, CMOS, DIMM-168	Synchronous DRAM Module, 8MX64, 7ns, CMOS, DIMM-168	Synchronous DRAM Module, 8MX64, 6.5ns, CMOS, DIMM-168	Synchronous DRAM Module, 8MX72, 7ns, CMOS, DIMM-168
Maker	IBM	IBM	IBM	IBM
Parts packaging code	DIMM	DIMM	DIMM	DIMM
package instruction	DIMM, DIMM168	DIMM, DIMM168	DIMM, DIMM168	DIMM, DIMM168
Contacts	168	168	168	168
Reach Compliance Code	unknown	unknown	unknown	unknown
ECCN code	EAR99	EAR99	EAR99	EAR99
access mode	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
Maximum access time	6.5 ns	7 ns	6.5 ns	7 ns
Maximum clock frequency (fCLK)	100 MHz	100 MHz	100 MHz	100 MHz
I/O type	COMMON	COMMON	COMMON	COMMON
JESD-30 code	R-XDMA-N168	R-XDMA-N168	R-XDMA-N168	R-XDMA-N168
memory density	603979776 bit	536870912 bit	536870912 bit	603979776 bit
Memory IC Type	SYNCHRONOUS DRAM MODULE	SYNCHRONOUS DRAM MODULE	SYNCHRONOUS DRAM MODULE	SYNCHRONOUS DRAM MODULE
memory width	72	64	64	72
Number of functions	1	1	1	1
Number of ports	1	1	1	1
Number of terminals	168	168	168	168
word count	8388608 words	8388608 words	8388608 words	8388608 words
character code	8000000	8000000	8000000	8000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C
organize	8MX72	8MX64	8MX64	8MX72
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
encapsulated code	DIMM	DIMM	DIMM	DIMM
Encapsulate equivalent code	DIMM168	DIMM168	DIMM168	DIMM168
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY
power supply	3.3 V	3.3 V	3.3 V	3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
refresh cycle	4096	4096	4096	4096
Maximum standby current	0.018 A	0.016 A	0.016 A	0.018 A
Maximum slew rate	1.395 mA	1.24 mA	1.24 mA	1.395 mA
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3 V	3 V	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	NO	NO	NO	NO
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	NO LEAD	NO LEAD	NO LEAD	NO LEAD
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL	DUAL

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