CY7C1529KV18-300BZI datasheet, PDF

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CY7C1529KV18-300BZI: DescriptionDDR SRAM, 8MX9, 0.45ns, CMOS, PBGA165, 15 X 13 MM, 1.40 MM HEIGHT, MO-216, FBGA-165; Categorystorage storage; File Size883KB，32 Pages; ManufacturerCypress Semiconductor

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CY7C1529KV18-300BZI Overview

DDR SRAM, 8MX9, 0.45ns, CMOS, PBGA165, 15 X 13 MM, 1.40 MM HEIGHT, MO-216, FBGA-165

CY7C1529KV18-300BZI Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Cypress Semiconductor
Parts packaging code	BGA
package instruction	15 X 13 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	0.45 ns
Other features	PIPELINED ARCHITECTURE
I/O type	SEPARATE
JESD-30 code	R-PBGA-B165
length	15 mm
memory density	75497472 bit
Memory IC Type	DDR SRAM
memory width	9
Number of functions	1
Number of terminals	165
word count	8388608 words
character code	8000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	8MX9
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
power supply	1.5/1.8,1.8 V
Certification status	Not Qualified
Maximum seat height	1.4 mm
Maximum standby current	0.28 A
Minimum standby current	1.7 V
Maximum slew rate	0.48 mA
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	13 mm
Base Number Matches	1

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CY7C1522KV18, CY7C1529KV18

CY7C1523KV18, CY7C1524KV18

72-Mbit DDR II SIO SRAM 2-Word

Burst Architecture

Features

■

Functional Description

The CY7C1522KV18, CY7C1529KV18, CY7C1523KV18, and

CY7C1524KV18 are 1.8V Synchronous Pipelined SRAMs,

equipped with DDR II SIO (Double Data Rate Separate I/O)

architecture. The DDR II SIO consists of two separate ports: the

read port and the write port to access the memory array. The

read port has data outputs to support read operations and the

write port has data inputs to support write operations. The DDR

II SIO has separate data inputs and data outputs to completely

eliminate the need to “turnaround” the data bus required with

common I/O devices. Access to each port is accomplished

through a common address bus. Addresses for read and write

are latched on alternate rising edges of the input (K) clock. Write

data is registered on the rising edges of both K and K. Read data

is driven on the rising edges of C and C if provided, or on the

rising edge of K and K if C/C are not provided. Each address

location is associated with two 8-bit words in the case of

CY7C1522KV18, two 9-bit words in the case of

CY7C1529KV18, two 18-bit words in the case of

CY7C1523KV18, and two 36-bit words in the case of

CY7C1524KV18 that burst sequentially into or out of the device.

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs are tightly matched to the

two output echo clocks CQ/CQ, eliminating the need to capture

data separately from each individual DDR II SIO SRAM in the

system design. Output data clocks (C/C) enable maximum

system clocking and data synchronization flexibility.

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

72 Mbit Density (8M x 8, 8M x 9, 4M x 18, 2M x 36)

333 MHz Clock for High Bandwidth

2-word Burst for reducing Address Bus Frequency

Double Data Rate (DDR) Interfaces

(data transferred at 666 MHz) at 333 MHz

Two Input Clocks (K and K) for precise DDR Timing

❐

SRAM uses rising edges only

Two Input Clocks for Output Data (C and C) to minimize Clock

Skew and Flight Time mismatches

Echo Clocks (CQ and CQ) simplify Data Capture in High Speed

Systems

Synchronous Internally Self timed Writes

DDR II operates with 1.5 Cycle Read Latency when DOFF is

asserted HIGH

Operates similar to DDR-I Device with 1 Cycle Read Latency

when DOFF is asserted LOW

1.8V Core Power Supply with HSTL Inputs and Outputs

Variable Drive HSTL Output Buffers

Expanded HSTL Output Voltage (1.4V–V

)

❐

Supports both 1.5V and 1.8V IO supply

Available in 165-ball FBGA Package (13 x 15 x 1.4 mm)

Offered in both Pb-free and non Pb-free Packages

JTAG 1149.1 compatible Test Access Port

Phase Locked Loop (PLL) for accurate Data Placement

■

Configurations

CY7C1522KV18 – 8M x 8

CY7C1529KV18 – 8M x 9

CY7C1523KV18 – 4M x 18

CY7C1524KV18 – 2M x 36

Table 1. Selection Guide

Description

Maximum Operating Frequency

Maximum Operating Current

x18

x36

333 MHz

333

510

520

640

300 MHz

300

480

490

600

250 MHz

250

420

430

530

200 MHz

200

370

380

450

167 MHz

167

340

400

Unit

MHz

Cypress Semiconductor Corporation

Document Number: 001-00438 Rev. *F

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised January 29, 2010

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