Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= 2.7V to 3.6V (MAX11607/MAX11609/MAX11611), V
DD
= 4.5V to 5.5V (MAX11606/MAX11608/MAX11610), V
REF
= 2.048V
(MAX11607/MAX11609/MAX11611), V
REF
= 4.096V (MAX11606/MAX11608/MAX11610), f
SCL
= 1.7MHz, T
A
= T
MIN
to T
MAX
, unless other-
wise noted. Typical values are at T
A
= +25°C. See Tables 1–5 for programming notation.) (Note 1)
PARAMETER
DC ACCURACY (Note 2)
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
Offset-Error Temperature
Coefficient
Gain Error
Gain-Temperature Coefficient
Channel-to-Channel Offset
Matching
Channel-to-Channel Gain
Matching
DYNAMIC PERFORMANCE (f
IN(SINE-WAVE)
= 10kHz, V
IN(P-P)
= V
REF
, f
SAMPLE
= 94.4ksps)
Signal-to-Noise Plus Distortion
Total Harmonic Distortion
Spurious Free Dynamic Range
Full-Power Bandwidth
Full-Linear Bandwidth
CONVERSION RATE
Conversion Time (Note 5)
t
CONV
Internal clock
External clock
Internal clock, SCAN[1:0] = 01
Throughput Rate
f
SAMPLE
Internal clock, SCAN[1:0] = 00
CS[3:0] = 1011 (MAX11610/MAX11611)
External clock
Track/Hold Acquisition Time
2
SYMBOL
CONDITIONS
MIN
10
TYP
MAX
UNITS
Bits
INL
DNL
(Note 3)
No missing codes over temperature
±1
±1
±1
LSB
LSB
LSB
ppm/°C
Relative to FSR
(Note 4)
Relative to FSR
0.3
±1
0.3
±0.1
±0.1
LSB
ppm/°C
LSB
LSB
SINAD
THD
SFDR
SINAD > 57dB
-3dB point
Up to the 5th harmonic
60
-70
70
3.0
5.0
6.8
10.6
53
53
94.4
800
dB
dB
dB
MHz
MHz
µs
ksps
ns
Maxim Integrated
MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I
2
C,
10-Bit ADCs in Ultra-Small Packages
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 2.7V to 3.6V (MAX11607/MAX11609/MAX11611), V
DD
= 4.5V to 5.5V (MAX11606/MAX11608/MAX11610), V
REF
= 2.048V
(MAX11607/MAX11609/MAX11611), V
REF
= 4.096V (MAX11606/MAX11608/MAX11610), f
SCL
= 1.7MHz, T
A
= T
MIN
to T
MAX
, unless other-
wise noted. Typical values are at T
A
= +25°C. See Tables 1–5 for programming notation.) (Note 1)
PARAMETER
Internal Clock Frequency
Aperture Delay (Note 6)
ANALOG INPUT (AIN0–AIN11)
Input-Voltage Range, Single-
Ended and Differential (Note 7)
Input Multiplexer Leakage Current
Input Capacitance
INTERNAL REFERENCE (Note 8)
Reference Voltage
Reference-Voltage Temperature
Coefficient
REF Short-Circuit Current
REF Source Impedance
EXTERNAL REFERENCE
REF Input-Voltage Range
REF Input Current
Input High Voltage
Input Low Voltage
Input Hysteresis
Input Current
Input Capacitance
Output Low Voltage
POWER REQUIREMENTS
Supply Voltage
V
DD
MAX11607/MAX11609/MAX11611
MAX11606/MAX11608/MAX11610
f
SAMPLE
= 94.4ksps
external clock
f
SAMPLE
= 40ksps
internal clock
Supply Current
I
DD
f
SAMPLE
= 10ksps
internal clock
f
SAMPLE
=1ksps
internal clock
Internal reference
External reference
Internal reference
External reference
Internal reference
External reference
Internal reference
External reference
2.7
4.5
900
670
530
230
380
60
330
6
0.5
10
3
SYMBOL
CONDITIONS
External clock, fast mode
External clock, high-speed mode
Unipolar
Bipolar
On/off leakage current, V
AIN_
= 0V or V
DD
MIN
TYP
2.8
60
30
MAX
UNITS
MHz
ns
t
AD
0
0
±0.01
22
MAX11607/MAX11609/MAX11611
MAX11606/MAX11608/MAX11610
1.968
3.939
2.048
4.096
25
V
REF
±V
REF
/2
±1
V
µA
pF
C
IN
V
REF
TCVREF
T
A
= +25°C
2.128
4.256
V
ppm/°C
2
1.5
mA
kΩ
V
REF
I
REF
V
IH
V
IL
V
HYST
I
IN
C
IN
V
OL
(Note 9)
f
SAMPLE
= 94.4ksps
1
V
DD
40
V
µA
V
DIGITAL INPUTS/OUTPUTS (SCL, SDA)
0.7 x V
DD
0.3 x V
DD
0.1 x V
DD
V
IN
= 0 to V
DD
15
I
SINK
= 3mA
0.4
3.6
5.5
1150
900
±10
V
V
µA
pF
V
V
µA
Shutdown (internal reference off)
Maxim Integrated
MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I
2
C,
10-Bit ADCs in Ultra-Small Packages
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 2.7V to 3.6V (MAX11607/MAX11609/MAX11611), V
DD
= 4.5V to 5.5V (MAX11606/MAX11608/MAX11610), V
REF
= 2.048V
(MAX11607/MAX11609/MAX11611), V
REF
= 4.096V (MAX11606/MAX11608/MAX11610), f
SCL
= 1.7MHz, T
A
= T
MIN
to T
MAX
, unless other-
wise noted. Typical values are at T
A
= +25°C. See Tables 1–5 for programming notation.) (Note 1)
PARAMETER
POWER REQUIREMENTS
Power-Supply Rejection Ratio
PSRR
Full-scale input (Note 10)
±0.01
±0.5
LSB/V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS (Figure 1)
(V
DD
= 2.7V to 3.6V (MAX11607/MAX11609/MAX11611), V
DD
= 4.5V to 5.5V (MAX11606/MAX11608/MAX11610), V
REF
= 2.048V
(MAX11607/MAX11609/MAX11611), V
REF
= 4.096V (MAX11606/MAX11608/MAX11610), f
SCL
= 1.7MHz, T
A
= T
MIN
to T
MAX
, unless other-
wise noted. Typical values are at T
A
= +25°C. See Tables 1–5 for programming notation.) (Note 1)
PARAMETER
Serial-Clock Frequency
Bus Free Time Between a
STOP (P) and a
START (S) Condition
Hold Time for START (S) Condition
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for a Repeated START
Condition (Sr)
Data Hold Time
Data Setup Time
Rise Time of Both SDA and SCL
Signals, Receiving
Fall Time of SDA Transmitting
Setup Time for STOP (P) Condition
Capacitive Load for Each Bus Line
Pulse Width of Spike Suppressed
Serial-Clock Frequency
Hold Time, Repeated START
Condition (Sr)
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for a Repeated START
Condition (Sr)
Data Hold Time
Data Setup Time
SYMBOL
f
SCL
t
BUF
t
HD,STA
t
LOW
t
HIGH
t
SU,STA
t
HD,DAT
t
SU,DAT
t
R
t
F
t
SU,STO
C
B
t
SP
f
SCLH
t
HD,STA
t
LOW
t
HIGH
t
SU
,
STA
t
HD
,
DAT
t
SU
,
DAT
(Note 11)
(Note 14)
160
320
120
160
0
10
150
Measured from 0.3V
DD
to 0.7V
DD
Measured from 0.3V
DD
to 0.7V
DD
(Note 12)
(Note 11)
1.3
0.6
1.3
0.6
0.6
0
100
20 + 0.1C
B
20 + 0.1C
B
0.6
400
50
1.7
300
300
900
CONDITIONS
MIN
TYP
MAX
400
UNITS
kHz
µs
µs
µs
µs
µs
ns
ns
ns
ns
µs
pF
ns
MHz
ns
ns
ns
ns
ns
ns
TIMING CHARACTERISTICS FOR FAST MODE
TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (C
B
= 400pF, Note 13)
4
Maxim Integrated
MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I
2
C,
10-Bit ADCs in Ultra-Small Packages
TIMING CHARACTERISTICS (Figure 1) (continued)
(V
DD
= 2.7V to 3.6V (MAX11607/MAX11609/MAX11611), V
DD
= 4.5V to 5.5V (MAX11606/MAX11608/MAX11610), V
REF
= 2.048V
(MAX11607/MAX11609/MAX11611), V
REF
= 4.096V (MAX11606/MAX11608/MAX11610), f
SCL
= 1.7MHz, T
A
= T
MIN
to T
MAX
, unless other-
wise noted. Typical values are at T
A
= +25°C. See Tables 1–5 for programming notation.) (Note 1)
PARAMETER
Rise Time of SCL Signal
(Current Source Enabled)
Rise Time of SCL Signal after
Acknowledge Bit
Fall Time of SCL Signal
Rise Time of SDA Signal
Fall Time of SDA Signal
Setup Time for STOP (P) Condition
Capacitive Load for Each Bus Line
Pulse Width of Spike Suppressed
SYMBOL
t
RCL
t
RCL1
t
FCL
t
RDA
t
FDA
t
SU
,
STO
C
B
t
SP
(Notes 11 and 14)
0
CONDITIONS
Measured from 0.3V
DD
to 0.7V
DD
Measured from 0.3V
DD
to 0.7V
DD
Measured from 0.3V
DD
to 0.7V
DD
Measured from 0.3V
DD
to 0.7V
DD
Measured from 0.3V
DD
to 0.7V
DD
(Note 12)
MIN
20
20
20
20
20
160
400
10
TYP
MAX
80
160
80
160
160
UNITS
ns
ns
ns
ns
ns
ns
pF
ns
Note 1:
All WLP devices are 100% production tested at T
A
= +25°C. Specifications over temperature limits are guaranteed by
design and characterization.
Note 2:
For DC accuracy, the MAX11606/MAX11608/MAX11610 are tested at V
DD
= 5V and the MAX11607/MAX11609/MAX11611
are tested at V
DD
= 3V. All devices are configured for unipolar, single-ended inputs.
Note 3:
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offsets have been calibrated.
Note 4:
Offset nulled.
Note 5:
Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. Conversion
time does not include acquisition time. SCL is the conversion clock in the external clock mode.
Note 6:
A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
Note 7:
The absolute input-voltage range for the analog inputs (AIN0–AIN11) is from GND to V
DD
.
Note 8:
When the internal reference is configured to be available at AIN_/REF (SEL[2:1] = 11), decouple AIN_/REF to GND with a
0.1µF capacitor and a 2kΩ series resistor (see the
Typical Operating Circuit).
Note 9:
ADC performance is limited by the converter’s noise floor, typically 300µV
P-P
.
Note 10:
Measured as follows for the MAX11607/MAX11609/MAX11611:
⎡
2
N
−
1
⎤
⎢
[
V
FS
(3.6V)
−
V
FS
(2.7V)
]
×
⎥
V
REF
⎦
⎣
(3.6V
−
2.7V)
and for the MAX11606/MAX11608/MAX11610, where N is the number of bits:
⎡
2
N
−
1
⎤
V
FS
(5.5V)
−
V
FS
(4.5V)
]
×
⎢
[
⎥
V
REF
⎦
⎣
(5.5V
−
4.5V)
Note 11:
A master device must provide a data hold time for SDA (referred to V
IL
of SCL) to bridge the undefined region of SCL’s
falling edge (see Figure 1).
Note 12:
The minimum value is specified at T
A
= +25°C.
Note 13:
C
B
= total capacitance of one bus line in pF.
Note 14:
f
SCL
must meet the minimum clock low time plus the rise/fall times.
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