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UPD4482361GF-A75Y

Description
Cache SRAM, 256KX36, 7.5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, LQFP-100
Categorystorage    storage   
File Size379KB,28 Pages
ManufacturerNEC Electronics
Download Datasheet Parametric View All

UPD4482361GF-A75Y Overview

Cache SRAM, 256KX36, 7.5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, LQFP-100

UPD4482361GF-A75Y Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerNEC Electronics
Parts packaging codeQFP
package instructionLQFP,
Contacts100
Reach Compliance Codecompliant
ECCN code3A991.B.2.A
Maximum access time7.5 ns
Other featuresFLOW-THROUGH ARCHITECTURE
JESD-30 codeR-PQFP-G100
JESD-609 codee0
length20 mm
memory density9437184 bit
Memory IC TypeCACHE SRAM
memory width36
Number of functions1
Number of terminals100
word count262144 words
character code256000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize256KX36
Package body materialPLASTIC/EPOXY
encapsulated codeLQFP
Package shapeRECTANGULAR
Package formFLATPACK, LOW PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum seat height1.7 mm
Maximum supply voltage (Vsup)3.465 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width14 mm
Base Number Matches1
DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD4482161, 4482181, 4482321, 4482361
8M-BIT CMOS SYNCHRONOUS FAST SRAM
FLOW THROUGH OPERATION
Description
The
µ
PD4482161 is a 524,288-word by 16-bit, the
µ
PD4482181 is a 524,288-word by 18-bit, the
µ
PD4482321 is a
262,144-word by 32-bit and the
µ
PD4482361 is a 262,144-word by 36-bit synchronous static RAM fabricated with
advanced CMOS technology using Full-CMOS six-transistor memory cell.
The
µ
PD4482161,
µ
PD4482181,
µ
PD4482321 and
µ
PD4482361 integrate unique synchronous peripheral circuitry, 2-bit
burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single
clock input (CLK).
The
µ
PD4482161,
µ
PD4482181,
µ
PD4482321 and
µ
PD4482361 are suitable for applications which require synchronous
operation, high speed, low voltage, high density and wide bit configuration, such as cache and buffer memory.
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”). In
the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal operation.
The
µ
PD4482161,
µ
PD4482181,
µ
PD4482321 and
µ
PD4482361 are packaged in 100-pin PLASTIC LQFP with a 1.4
mm package thickness for high density and low capacitive loading.
Features
3.3 V or 2.5 V core supply
Synchronous operation
Operating temperature : T
A
= 0 to 70
°C
(-A65, -A75, -A85, -C75, -C85)
T
A
=
−40
to
+85 °C
(-A65Y, -A75Y, -A85Y, -C75Y, -C85Y)
Internally self-timed write control
Burst read / write : Interleaved burst and linear burst sequence
Fully registered inputs for flow through operation
All registers triggered off positive clock edge
3.3 V or 2.5 V LVTTL Compatible : All inputs and outputs
Fast clock access time : 6.5 ns (133 MHz), 7.5 ns (117 MHz), 8.5 ns (100 MHz)
Asynchronous output enable : /G
Burst sequence selectable : MODE
Sleep mode : ZZ (ZZ = Open or Low : Normal operation)
Separate byte write enable : /BW1 to /BW4, /BWE (
µ
PD4482321,
µ
PD4482361)
/BW1, /BW2, /BWE (
µ
PD4482161,
µ
PD4482181)
Global write enable : /GW
Three chip enables for easy depth expansion
Common I/O using three state outputs
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M14521EJ3V0DS00 (3rd edition)
Date Published December 2002 NS CP(K)
Printed in Japan
The mark
shows major revised points.
2000
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