EEWORLDEEWORLDEEWORLD

Part Number

Search

BZV25/A1010/16

Description
Mains Power Connector, 10A, 250VAC, Male
CategoryThe connector    The connector   
File Size78KB,1 Pages
ManufacturerBULGIN
Websitehttp://www.bulgin.co.uk/
Environmental Compliance
Download Datasheet Parametric View All

BZV25/A1010/16 Overview

Mains Power Connector, 10A, 250VAC, Male

BZV25/A1010/16 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerBULGIN
Reach Compliance Codecompliant
Connector typeMAINS POWER CONNECTOR
Contact to complete cooperationNOT SPECIFIED
Contact point genderMALE
Contact materialNOT SPECIFIED
Coupling typeSNAP
DIN complianceNO
IEC complianceNO
MIL complianceNO
Power Connector Ratings10A, 250VAC
Manufacturer's serial numberBZV
Installation typePANEL
Total number of contacts3
Base Number Matches1
[GD32L233C-START Review] 3. GPIO, EXTI
This time, we use the four LEDs and the "Wakeup" button on the GD32L233C-START board to conduct experiments, and learn about the GPIO and EXTI (external interrupt resources) of GD32L233CCT6 through si...
lising GD32 MCU
Some special uses of AD6
1. Globally modify the character size. Generally speaking, the component number and key parameters are marked near the components of the formal PCB,but some pure SMD circuit boards are relatively smal...
破茧佼龙 MCU
XILINX ISE 14.6 Failed to create temporary project! !
Open ISE, and a dialog box "Project Open Failed" will pop up first. Close it and then click New Project, and then "Failed to create temporary project" will appear, and another dialog box will pop up a...
daiwenzhou FPGA/CPLD
Chinese caller ID device based on DTMF format!
[i=s]This post was last edited by paulhyde on 2014-9-15 03:39[/i] [b][color=#000099][/color][/b] [url=http://bbs.cepark.com/attachment.php?aid=MjgzMnwwNzgwODIzOXwxMjY3MzYwMDEzfGFiNzZYdmI4MXN2UzZVcXJaY...
gina Electronics Design Contest
High-speed AD data acquisition, asynchronous FIFO, or dual-port RAM
RT acts as an oscilloscope, FPGA collects data and sends it to STM32 for display. Experienced friends please give me some advice....
523335234 FPGA/CPLD
Modification of sensitive variable table after ISE VHDL synthesis
After synthesis, I added sensitive variables according to the warning, but the program does not run. I want to know, after synthesis, I must remove the latch according to the warning, but must I add s...
timdong FPGA/CPLD

Technical ResourceMore

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1276  764  1935  1527  1063  26  16  39  31  22 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号