MCP621/2/5
20 MHz, 2.5 mA Op Amps with mCal
Features
•
•
•
•
•
•
•
•
•
Gain Bandwidth Product: 20 MHz (typical)
Short Circuit Current: 70 mA (typical)
Noise: 13 nV/√Hz (typical, at 1 MHz)
Calibrated Input Offset: ±200 µV (maximum)
Rail-to-Rail Output
Slew Rate: 10 V/µs (typical)
Supply Current: 2.5 mA (typical)
Power Supply: 2.5V to 5.5V
Extended Temperature Range: -40°C to +125°C
Description
The Microchip Technology, Inc. MCP621/2/5 family of
operational amplifiers features low offset. At power up,
these op amps are self-calibrated using mCal. Some
package options also provide a calibration/chip select
pin (CAL/CS) that supports a low power mode of
operation, with offset calibration at the time normal
operation is re-started. These amplifiers are optimized
for high speed, low noise and distortion, single-supply
operation with rail-to-rail output and an input that
includes the negative rail.
This family is offered in single with CAL/CS pin
(MCP621), dual (MCP622) and dual with CAL/CS pins
(MCP625). All devices are fully specified from -40°C to
+125°C.
Typical Applications
•
•
•
•
Driving A/D Converters
Power Amplifier Control Loops
Barcode Scanners
Optical Detector Amplifier
Typical Application Circuit
V
DD
/2
V
IN
R
1
R
3
R
2
V
OUT
MCP62X
R
L
Design Aids
•
•
•
•
•
•
SPICE Macro Models
FilterLab
®
Software
Mindi™ Circuit Designer & Simulator
Microchip Advanced Part Selector (MAPS)
Analog Demonstration and Evaluation Boards
Application Notes
Power Driver with High Gain
Package Types
MCP621
SOIC
NC 1
V
IN
– 2
V
IN
+ 3
V
SS
4
8 CAL/CS
7 V
DD
6 V
OUT
5 V
CAL
MCP622
3x3 DFN *
V
OUTA
1
V
INA
– 2
V
INA
+ 3
V
SS
4
EP
9
8 V
DD
7 V
OUTB
6 V
INB
–
5 V
INB
+
MCP625
3x3 DFN *
V
OUTA
1
V
INA
– 2
V
INA
+ 3
V
SS
4
CAL
A
/CS
A
5
EP
11
10 V
DD
9 V
OUTB
8 V
INB
–
7 V
INB
+
6 CAL
B
/CS
B
MCP622
SOIC
V
OUTA
1
V
INA
– 2
V
INA
+ 3
V
SS
4
8 V
DD
7 V
OUTB
6 V
INB
–
5 V
INB
+
MCP625
MSOP
V
OUTA
1
V
INA
– 2
V
INA
+ 3
V
SS
4
CAL
A
/CS
A
5
10 V
DD
9 V
OUTB
8 V
INB
–
7 V
INB
+
6 CAL
B
/CS
B
* Includes Exposed Thermal Pad (EP); see
Table 3-1.
©
2009 Microchip Technology Inc.
DS22188A-page 1
MCP621/2/5
NOTES:
DS22188A-page 2
©
2009 Microchip Technology Inc.
MCP621/2/5
1.0
1.1
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
†
Notice:
Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
††
See
Section 4.2.2 “Input Voltage and Current Limits”.
V
DD
– V
SS
.......................................................................6.5V
Current at Input Pins ....................................................±2 mA
Analog Inputs (V
IN
+ and V
IN
–) †† . V
SS
– 1.0V to V
DD
+ 1.0V
All other Inputs and Outputs .......... V
SS
– 0.3V to V
DD
+ 0.3V
Output Short Circuit Current ................................ Continuous
Current at Output and Supply Pins ..........................±150 mA
Storage Temperature ...................................-65°C to +150°C
Max. Junction Temperature ........................................ +150°C
ESD protection on all pins (HBM, MM)
................≥
1 kV, 200V
1.2
Specifications
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics:
Unless otherwise indicated, T
A
= +25°C, V
DD
= +2.5V to +5.5V, V
SS
= GND, V
CM
= V
DD
/3,
V
OUT
≈
V
DD
/2, V
L
= V
DD
/2, R
L
= 2 kΩ to V
L
and CAL/CS = V
SS
(refer to
Figure 1-2).
Parameters
Input Offset
Input Offset Voltage
Input Offset Voltage Trim Step Size
Input Offset Voltage Drift
Power Supply Rejection Ratio
Input Current and Impedance
Input Bias Current
Across Temperature
Across Temperature
Input Offset Current
Common Mode Input Impedance
Differential Input Impedance
Common Mode
Common-Mode Input Voltage Range
Common-Mode Rejection Ratio
Open-Loop Gain
DC Open-Loop Gain (large signal)
Output
Maximum Output Voltage Swing
Sym
V
OS
V
OSTRM
ΔV
OS
/ΔT
A
PSRR
I
B
I
B
I
B
I
OS
Z
CM
Z
DIFF
V
CMR
CMRR
CMRR
A
OL
A
OL
V
OL
, V
OH
V
OL
, V
OH
Min
-200
—
—
61
—
—
—
—
—
—
V
SS
−
0.3
65
68
88
94
V
SS
+ 20
V
SS
+ 40
±40
±35
Typ
—
37
±2.0
76
5
100
1700
±10
10
13
||9
10 ||2
—
81
84
117
126
—
—
±85
±70
13
Max
+200
200
—
—
—
—
5,000
—
—
—
V
DD
−
1.3
—
—
—
—
V
DD
−
20
V
DD
−
40
±130
±110
Units
µV
µV
dB
pA
pA
pA
pA
Ω||pF
Ω||pF
V
dB
dB
dB
dB
mV
mV
mA
mA
(Note 3)
Conditions
After calibration
(Note 1)
(Note 2)
µV/°C T
A
= -40°C to +125°C
T
A
= +85°C
T
A
= +125°C
V
DD
= 2.5V, V
CM
= -0.3 to 1.2V
V
DD
= 5.5V, V
CM
= -0.3 to 4.2V
V
DD
= 2.5V, V
OUT
= 0.3V to 2.2V
V
DD
= 5.5V, V
OUT
= 0.3V to 5.2V
V
DD
= 2.5V, G = +2,
0.5V Input Overdrive
V
DD
= 5.5V, G = +2,
0.5V Input Overdrive
V
DD
= 2.5V
(Note 4)
V
DD
= 5.5V
(Note 4)
Output Short Circuit Current
Note 1:
2:
3:
4:
I
SC
I
SC
Describes the offset (under the specified conditions) right after power up, or just after the CAL/CS pin is toggled. Thus,
1/f noise effects (an apparent wander in V
OS
; see
Figure 2-35)
are not included.
Increment between adjacent V
OS
trim points;
Figure 2-3
shows how this affects the V
OS
repeatability.
See
Figure 2-6
and
Figure 2-7
for temperature effects.
The I
SC
specifications are for design guidance only; they are not tested.
©
2009 Microchip Technology Inc.
DS22188A-page 3
MCP621/2/5
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics:
Unless otherwise indicated, T
A
= +25°C, V
DD
= +2.5V to +5.5V, V
SS
= GND, V
CM
= V
DD
/3,
V
OUT
≈
V
DD
/2, V
L
= V
DD
/2, R
L
= 2 kΩ to V
L
and CAL/CS = V
SS
(refer to
Figure 1-2).
Parameters
Calibration Input
Calibration Input Voltage Range
Internal Calibration Voltage
Input Impedance
Power Supply
Supply Voltage
Quiescent Current per Amplifier
POR Input Threshold, Low
POR Input Threshold, High
Note 1:
2:
3:
4:
Sym
V
CALRNG
V
CAL
Z
CAL
V
DD
I
Q
V
PRL
V
PRH
Min
V
SS
+ 0.1
0.323V
DD
—
2.5
1.2
1.15
—
Typ
—
0.333V
DD
100 || 5
—
2.5
1.40
1.40
Max
V
DD
– 1.4
0.343V
DD
—
5.5
3.6
—
1.65
Units
mV
kΩ||pF
V
mA
V
V
I
O
= 0
Conditions
V
CAL
pin externally driven
V
CAL
pin open
Describes the offset (under the specified conditions) right after power up, or just after the CAL/CS pin is toggled. Thus,
1/f noise effects (an apparent wander in V
OS
; see
Figure 2-35)
are not included.
Increment between adjacent V
OS
trim points;
Figure 2-3
shows how this affects the V
OS
repeatability.
See
Figure 2-6
and
Figure 2-7
for temperature effects.
The I
SC
specifications are for design guidance only; they are not tested.
AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics:
Unless otherwise indicated, T
A
= +25°C, V
DD
= +2.5V to +5.5V, V
SS
= GND, V
CM
= V
DD
/2,
V
OUT
≈
V
DD
/2, V
L
= V
DD
/2, R
L
= 2 kΩ to V
L
, C
L
= 50 pF and CAL/CS = V
SS
(refer to
Figure 1-2).
Parameters
AC Response
Gain Bandwidth Product
Phase Margin
Open-Loop Output Impedance
AC Distortion
Total Harmonic Distortion plus Noise
Step Response
Rise Time, 10% to 90%
Slew Rate
Noise
Input Noise Voltage
Input Noise Voltage Density
Input Noise Current Density
Sym
GBWP
PM
R
OUT
THD+N
Min
—
—
—
—
Typ
20
60
15
0.0018
Max
—
—
—
—
Units
MHz
°
Ω
%
G = +1
Conditions
G = +1, V
OUT
= 2V
P-P
, f = 1 kHz,
V
DD
= 5.5V, BW = 80 kHz
G = +1, V
OUT
= 100 mV
P-P
G = +1
f = 0.1 Hz to 10 Hz
f = 1 kHz
t
r
SR
E
ni
e
ni
i
ni
—
—
—
—
13
10
20
13
4
—
—
—
—
—
ns
V/µs
µV
P-P
fA/√Hz
nV/√Hz f = 1 MHz
DIGITAL ELECTRICAL SPECIFICATIONS
Electrical Characteristics:
Unless otherwise indicated, T
A
= +25°C, V
DD
= +2.5V to +5.5V, V
SS
= GND, V
CM
= V
DD
/2,
V
OUT
≈
V
DD
/2, V
L
= V
DD
/2, R
L
= 2 kΩ to V
L
, C
L
= 50 pF and CAL/CS = V
SS
(refer to
Figure 1-1
and
Figure 1-2).
Parameters
CAL/CS Low Specifications
CAL/CS Logic Threshold, Low
Note 1:
2:
3:
Sym
Min
Typ
Max
Units
Conditions
V
IL
V
SS
—
0.2V
DD
V
The MCP622 has its CAL/CS input internally pulled down to V
SS
(0V).
This time ensures that the internal logic recognizes the edge. However, for the rising edge case, if CAL/CS is raised
before the calibration is complete, the calibration will be aborted and the part will return to low power mode.
For the MCP625 dual, there is an additional constraint. CAL
A
/CS
A
and CAL
B
/CS
B
can be toggled simultaneously
(within a time much smaller than t
CSU
) to make both op amps perform the same function simultaneously. If they are
toggled independently, then CAL
A
/CS
A
(CAL
B
/CS
B
) cannot be allowed to toggle while op amp B (op amp A) is in
calibration mode; allow more than the maximum t
CON
time (8 ms) before the other side is toggled.
DS22188A-page 4
©
2009 Microchip Technology Inc.
MCP621/2/5
DIGITAL ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics:
Unless otherwise indicated, T
A
= +25°C, V
DD
= +2.5V to +5.5V, V
SS
= GND, V
CM
= V
DD
/2,
V
OUT
≈
V
DD
/2, V
L
= V
DD
/2, R
L
= 2 kΩ to V
L
, C
L
= 50 pF and CAL/CS = V
SS
(refer to
Figure 1-1
and
Figure 1-2).
Parameters
CAL/CS Input Current, Low
CAL/CS High Specifications
CAL/CS Logic Threshold, High
CAL/CS Input Current, High
GND Current
Sym
I
CSL
V
IH
I
CSH
I
SS
I
SS
I
SS
I
SS
Min
—
Typ
0
Max
—
Units
nA
CAL/CS = 0V
Conditions
0.8V
DD
—
-3.5
-8
-5
-10
—
—
—
100
0.7
-1.8
-4
-2.5
-5
5
50
200
200
V
DD
—
—
—
—
—
—
—
—
300
V
µA
µA
µA
µA
µA
MΩ
nA
ns
ms
CAL/CS = V
DD
, T
A
= 125°C
G = +1 V/V, V
L
= V
SS
,
V
DD
= 2.5V to 0V step to V
OUT
= 0.1 (2.5V)
G = +1 V/V, V
L
= V
SS
,
V
DD
= 0V to 2.5V step to V
OUT
= 0.9 (2.5V)
CAL/CS = V
DD
Single, CAL/CS = V
DD
= 2.5V
Single, CAL/CS = V
DD
= 5.5V
Dual, CAL/CS = V
DD
= 2.5V
Dual, CAL/CS = V
DD
= 5.5V
CAL/CS Internal Pull Down Resistor
Amplifier Output Leakage
POR Dynamic Specifications
V
DD
Low to Amplifier Off Time
(output goes High-Z)
V
DD
High to Amplifier On Time
(including calibration)
CAL/CS Dynamic Specifications
CAL/CS Input Hysteresis
CAL/CS Setup Time
(between CAL/CS edges)
CAL/CS High to Amplifier Off Time
(output goes High-Z)
CAL/CS Low to Amplifier On Time
(including calibration)
Note 1:
2:
3:
R
PD
I
O(LEAK)
t
POFF
t
PON
V
HYST
t
CSU
t
COFF
t
CON
—
1
—
—
0.25
—
200
5
—
—
—
8
V
µs
ns
ms
G = +1 V/V, V
L
= V
SS
(Notes 2, 3)
CAL/CS = 0.8V
DD
to V
OUT
= 0.1 (V
DD
/2)
G = +1 V/V, V
L
= V
SS
,
CAL/CS = 0.8V
DD
to V
OUT
= 0.1 (V
DD
/2)
G = +1 V/V, V
L
= V
SS
,
CAL/CS = 0.2V
DD
to V
OUT
= 0.9 (V
DD
/2)
The MCP622 has its CAL/CS input internally pulled down to V
SS
(0V).
This time ensures that the internal logic recognizes the edge. However, for the rising edge case, if CAL/CS is raised
before the calibration is complete, the calibration will be aborted and the part will return to low power mode.
For the MCP625 dual, there is an additional constraint. CAL
A
/CS
A
and CAL
B
/CS
B
can be toggled simultaneously
(within a time much smaller than t
CSU
) to make both op amps perform the same function simultaneously. If they are
toggled independently, then CAL
A
/CS
A
(CAL
B
/CS
B
) cannot be allowed to toggle while op amp B (op amp A) is in
calibration mode; allow more than the maximum t
CON
time (8 ms) before the other side is toggled.
TEMPERATURE SPECIFICATIONS
Electrical Characteristics:
Unless otherwise indicated, all limits are specified for: V
DD
= +2.5V to +5.5V, V
SS
= GND.
Parameters
Temperature Ranges
Specified Temperature Range
Operating Temperature Range
Storage Temperature Range
Thermal Package Resistances
Thermal Resistance, 8L-3x3 DFN
Thermal Resistance, 8L-SOIC
Thermal Resistance, 10L-3x3 DFN
Thermal Resistance, 10L-MSOP
Note 1:
2:
Sym
T
A
T
A
T
A
θ
JA
θ
JA
θ
JA
θ
JA
Min
-40
-40
-65
—
—
—
—
Typ
—
—
—
60
140.9
57
202
Max
+125
+125
+150
—
—
—
—
Units
°C
°C
°C
°C/W
°C/W
°C/W
°C/W
(Note 2)
(Note 2)
(Note 1)
Conditions
Operation must not cause T
J
to exceed Maximum Junction Temperature specification (150°C).
Measured on a standard JC51-7, four layer printed circuit board with ground plane and vias.
©
2009 Microchip Technology Inc.
DS22188A-page 5
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