DP8417D-70 datasheet, PDF - EEWORLD Datasheet

DP8417D-70: Description256KX1, DRAM CONTROLLER, CDIP48, SIDE BRAZED, CERAMIC, DIP-48; CategoryThe embedded processor and controller Microcontrollers and processors; File Size970KB，25 Pages; ManufacturerTexas Instruments; Websitehttp://www.ti.com.cn/

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DP8417D-70 Overview

256KX1, DRAM CONTROLLER, CDIP48, SIDE BRAZED, CERAMIC, DIP-48

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Texas Instruments
package instruction	DIP, DIP48,.6
Reach Compliance Code	unknown
Address bus width	18
boundary scan	NO
maximum clock frequency	70 MHz
External data bus width
JESD-30 code	R-CDIP-T48
JESD-609 code	e0
low power mode	NO
memory organization	256K X 1
Number of blocks	4
Number of terminals	48
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP
Encapsulate equivalent code	DIP48,.6
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Certification status	Not Qualified
Maximum seat height	5.08 mm
Maximum slew rate	240 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	NO
technology	BIPOLAR
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15.24 mm
uPs/uCs/peripheral integrated circuit type	MEMORY CONTROLLER, DRAM
Base Number Matches	1

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