Intel
®
Xeon
™
Processor MP with up to 2-MB L3
Cache (on the 0.13 Micron Process)
Datasheet
Product Features
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Available at 1.50, 1.90, and 2 GHz
Multi-processing server support
Binary compatible with applications
running on previous members of the Intel
®
IA32 microprocessor line
Intel
®
NetBurst™ microarchitecture
Hyper-Threading Technology
— Hardware support for multi-threaded
applications
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400 MHz System bus
— Bandwidth up to 3.2 GB/second
512
-
KB Advanced Transfer L2 Cache (on-
die, full speed Level 2 cache) with 8-way
associativity and Error Correcting Code
(ECC)
1-MB or 2-MB L3 Cache (on-die, full
speed Level 3 cache) with 8-way
associativity and Error Correcting Code
(ECC)
Enables system support of up to 64 GB of
physical memory
Streaming SIMD Extensions 2 (SSE2)
— 144 new instructions for double-precision
floating point operations, media/video
streaming, and secure transactions
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Rapid Execution Engine: Arithmetic Logic
Units (ALUs) run at twice the processor
core frequency
Hyper-Pipelined Technology
Advance Dynamic Execution
— Very deep out-of-order execution
— Enhanced branch prediction
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Enhanced floating point and multimedia
unit for enhanced video, audio, encryption,
and 3D performance
Power Management capabilities
— System Management mode
— Multiple low-power states
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Level 1 Execution Trace Cache stores 12 K
micro-ops and removes decoder latency
from main execution loops
— Includes 8- KB Level 1 data cache
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Advanced System Management Features
— System Management Bus
— Processor Information ROM (PIROM)
— OEM Scratch EEPROM
— Thermal Monitor
— Machine Check Architecture (MCA)
The Intel
®
Xeon™ processor MP with up to 2
-
MB L3 cache on the 0.13 micron process is
designed for high-performance multi-processor server applications. Based on the Intel
®
NetBurst™ microarchitecture and the new Hyper-Threading Technology, it is binary compatible
with previous Intel Architecture (IA-32) processors. The Intel Xeon processor MP with up to 2
-
MB L3 cache is scalable to four processors in a multiprocessor system providing exceptional
performance for applications running on advanced operating systems such as Microsoft
Windows* XP and Windows* 2000 operating systems, Linux*, and UNIX*. The Intel Xeon
processor MP with up to 2 MB L3 cache delivers compute power at unparalleled value and
flexibility for internet infrastructure and departmental server applications. The Intel NetBurst
microarchitecture and Hyper-Threading Technology deliver outstanding performance and
headroom for peak internet server workloads, resulting in faster response times, support for
more users, and improved scalability.
Document Number: 251931-001
November 2002
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS
OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS
DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL
ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO
SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A
PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future
changes to them.
The Intel
®
Xeon
™
processor MP with up to 2-MB L3 Cache may contain design defects or errors known as errata which may
cause the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
I
2
C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I
2
C bus/protocol and was developed
by Intel. Implementations of the I
2
C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including
Philips Electronics N.V. and North American Philips Corporation.
Intel, Pentium, Pentium III Xeon, Intel Xeon and Intel NetBurst are trademarks or registered trademarks of Intel Corporation or its
subsidiaries in the United States and other countries.
* Other names and brands may be claimed as the property of others.
Copyright © 2002 Intel Corporation
Datasheet
Contents
Contents
1
Introduction
................................................................................................................11
1.1
1.2
Terminology.........................................................................................................13
1.1.1 Processor Packaging Terminology.........................................................13
References ..........................................................................................................14
System Bus and GTLREF ...................................................................................15
Power and Ground Pins ......................................................................................15
Decoupling Guidelines ........................................................................................16
2.3.1 VCC Decoupling .....................................................................................16
2.3.2 System Bus AGTL+ Decoupling.............................................................16
System Bus Clock (BCLK[1:0]) and Processor Clocking ....................................16
2.4.1
Bus Clock ..............................................................................................17
PLL Filter .............................................................................................................18
2.5.1 Mixing Processors ..................................................................................19
Voltage Identification ..........................................................................................20
2.6.1 Mixing Processors of Different Voltages ................................................21
Reserved or Unused Pins ...................................................................................22
System Bus Signal Groups .................................................................................22
Asynchronous GTL+ Signals...............................................................................24
Maximum Ratings................................................................................................24
Processor DC Specifications...............................................................................25
AGTL+ System Bus Specifications .....................................................................30
System Bus AC Specifications ............................................................................31
Processor AC Timing Waveforms .......................................................................36
System Bus Clock (BCLK) Signal Quality Specifications and Measurement
Guidelines ...........................................................................................................47
System Bus Signal Quality Specifications and Measurement Guidelines...........48
System Bus Signal Quality Specifications and Measurement Guidelines...........51
3.3.1 Overshoot/Undershoot Guidelines .........................................................51
3.3.2 Overshoot/Undershoot Magnitude .........................................................52
3.3.3 Overshoot/Undershoot Pulse Duration...................................................52
3.3.4 Activity Factor .........................................................................................52
3.3.5 Reading Overshoot/Undershoot Specification Tables............................53
3.3.6 Determining if a System Meets the Overshoot/Undershoot
Specifications .........................................................................................53
Mechanical Specifications ...................................................................................59
Package Load Specifications ..............................................................................64
Insertion Specifications .......................................................................................64
Mass Specifications.............................................................................................64
Materials..............................................................................................................65
Markings..............................................................................................................65
Pinout Diagram....................................................................................................66
2
Electrical Specifications
........................................................................................15
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
3
System Bus Signal Quality Specifications
....................................................47
3.1
3.2
3.3
4
Mechanical Specifications
....................................................................................57
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Datasheet
3
Contents
5
Thermal Specifications
.......................................................................................... 69
5.1
5.2
Thermal Specifications........................................................................................ 71
Measurements for Thermal Specifications.......................................................... 73
5.2.1 Processor Case Temperature Measurement ......................................... 73
Power-On Configuration Options ........................................................................ 75
Clock Control and Low Power States.................................................................. 75
6.2.1 Normal State—State 1 ........................................................................... 75
6.2.2 AutoHALT Powerdown State—State 2 .................................................. 76
6.2.3 Stop-Grant State—State 3 ..................................................................... 77
6.2.4 HALT/Grant Snoop State—State 4 ........................................................ 77
6.2.5 Sleep State—State 5.............................................................................. 77
6.2.6 Bus Response during Low Power States ............................................... 78
Thermal Monitor .................................................................................................. 78
6.3.1 Thermal Diode........................................................................................ 79
System Management Bus (SMBus) Interface ..................................................... 79
6.4.1 Processor Information ROM (PIROM).................................................... 80
6.4.2 Scratch EEPROM .................................................................................. 83
6.4.3 PIROM and Scratch EEPROM Supported SMBus Transactions ........... 83
6.4.4 SMBus Thermal Sensor ......................................................................... 83
6.4.5 Thermal Sensor Supported SMBus Transactions .................................. 84
6.4.6 SMBus Thermal Sensor Registers ......................................................... 86
6.4.6.1 Thermal Reference Registers ................................................... 86
6.4.6.2 Thermal Limit Registers ............................................................ 87
6.4.6.3 Status Register.......................................................................... 87
6.4.6.4 Configuration Register............................................................... 87
6.4.6.5 Conversion Rate Registers ....................................................... 88
6.4.7 SMBus Thermal Sensor Alert Interrupt .................................................. 88
6.4.8 SMBus Device Addressing..................................................................... 89
Introduction ......................................................................................................... 91
Mechanical Specifications................................................................................... 92
7.2.1 Boxed Processor Heatsink Dimensions ................................................. 92
7.2.2 Boxed Processor Heatsink Weight......................................................... 92
7.2.3 Boxed Processor Retention Mechanism and Heatsink Supports........... 92
Boxed Processor Requirements ......................................................................... 95
7.3.1 Intel
®
Xeon™ Processor MP on the 0.13 Micron Process
Processor ............................................................................................... 95
Thermal Specifications........................................................................................ 95
7.4.1 Boxed Processor Cooling Requirements ............................................... 95
Logic Analyzer Interface (LAI)............................................................................. 97
8.1.1 Mechanical Considerations .................................................................... 97
8.1.2 Electrical Considerations........................................................................ 97
Intel
®
Xeon™ Processor MP on the 0.13 Micron Process Processor Pin
Assignments........................................................................................................ 99
6
Features
....................................................................................................................... 75
6.1
6.2
6.3
6.4
7
Boxed Processor Specifications
....................................................................... 91
7.1
7.2
7.3
7.4
8
Debug Tools Specifications
................................................................................. 97
8.1
9
Pin Listing and Signal Definitions
..................................................................... 99
9.1
4
Datasheet
Contents
9.2
9.1.1 Pin Listing by Pin Number ....................................................................108
Signal Definitions...............................................................................................117
Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Typical VCCIOPLL, VCCA and VSSA Power Distribution ..................................18
Phase Lock Loop (PLL) Filter Requirements ......................................................19
Intel
®
Xeon™ Processor MP on the 0.13 Micron Process Processor
Voltage-Current Projections ................................................................................26
Electrical Test Circuit...........................................................................................36
TCK Clock Waveform..........................................................................................37
Differential Clock Waveform................................................................................37
Differential Clock Crosspoint Specification..........................................................38
System Bus Common Clock Valid Delay Timing Waveform ...............................38
System Bus Source Synchronous 2X (Address) Timing Waveform....................39
System Bus Source Synchronous 4X (Data) Timing Waveform .........................40
System Bus Reset and Configuration Timing Waveform ....................................41
Power-On Reset and Configuration Timing Waveform .......................................41
TAP Valid Delay Timing Waveform .....................................................................42
Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing
Waveform ............................................................................................................42
THERMTRIP# to Vcc Timing...............................................................................42
SMBus Timing Waveform....................................................................................43
SMBus Valid Delay Timing Waveform ................................................................43
Example 3.3 Volt/SM_VCC Sequencing .............................................................44
FERR#/PBE# Valid Delay Timing .......................................................................45
BCLK[1:0] Signal Integrity Waveform..................................................................48
Low-to-High System Bus Receiver Ringback Tolerance for AGTL+ and
Asynchronous GTL+ Buffers ...............................................................................49
High-to-Low System Bus Receiver Ringback Tolerance for AGTL+ and
Asynchronous GTL+ Buffers ...............................................................................49
Low-to-High System Bus Receiver Ringback Tolerance for PWRGOOD and
TAP Buffers .........................................................................................................50
High-to-Low System Bus Receiver Ringback Tolerance for PWRGOOD and
TAP Buffers .........................................................................................................51
Maximum Acceptable Overshoot/Undershoot Waveform ...................................56
Intel
®
Xeon™ Processor MP on the 0.13 Micron Process Processor and
Intel
®
Xeon™ Processor with 512-KB L2 Cache in INT-mPGA Package -
Assembly Drawing (Including Socket).................................................................58
Intel
®
Xeon™ Processor MP on the 0.13 Micron Process Processor
Package Top View Component Placement Detail...............................................59
Intel
®
Xeon™ Processor MP on the 0.13 Micron Process Processor
Package Drawing ................................................................................................59
Intel
®
Xeon™ Processor MP on the 0.13 Micron Process Processor
Top View - Component Keep-In ..........................................................................61
Intel
®
Xeon™ Processor MP on the 0.13 Micron Process Processor and
Intel
®
Xeon™ Processor with 512-KB L2 Cache in INT-mPGA Package -
Cross Section View - Pin Side Component Keep-In ...........................................61
Datasheet
5
DSP and ARM Processors
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