ACT6330
Rev0, 02-Apr-08
Dual PWM Step-Up DC/DCs in TQFN33
FEATURES
•
Multiple Patents Pending
•
Two Integrated Regulators
−
PWM Step-Up DC/DC with OVP for WLED
Bias
−
PWM Step-Up DC/DC Converter with OVP
GENERAL DESCRIPTION
The patent-pending ACT6330 integrates two step-
up DC/DC into a single, thin, space-saving package
to provide a cost-effective, highly-efficient
ActivePMU
TM
power management solution. This device is ideal for
a wide range of portable handheld equipment that
can benefit from the advantages of
ActivePMU
tech-
nology but does not require a high level of integra-
tion.
REG1 and REG2 are fixed-frequency, current mode
PWM step-up DC/DC converter. REG1 is optimized
for high-efficiency WLED bias applications. REG2 is
optimized for voltage regulation applications, while
together these output can provide a complete TFT
bias and backlighting solution for portable handheld
equipment.
The ACT6330 is available in a tiny 3mm x 3mm 16
pin Thin-QFN package that is just 0.75mm thin.
•
Independent Enable/Disable Control
•
Minimal External Components
•
3×3mm, Thin-QFN (TQFN33-16) Package
−
Only 0.75mm Height
−
RoHS Compliant
APPLICATIONS
•
•
•
•
Portable Devices and PDAs
MP3/MP4 Players
Wireless Handhelds
GPS Receivers
SYSTEM BLOCK DIAGRAM
Battery
REG1
Step-Up
DC/DC
System
Control
OUT1
WLED Bias
Up to 18 LEDs
ON1
ON2
Pb-free
REG2
ACT6330
Active
Step-Up
DC/DC
OUT2
Up to 20V
PMU
TM
Innovative Power
TM
ActivePMU
TM
-1-
www.active-semi.com
Copyright © 2008 Active-Semi, Inc.
is a trademark of Active-Semi.
ACT6330
FUNCTIONAL BLOCK DIAGRAM
Rev0, 02-Apr-08
ACT6330
IN
UVLO
To Battery
SW1
OVP1
OUT1
ON1
REG1
FB1
GP12
ON2
SW2
OVP2
REG2
FB2
GP12
To Battery
OUT2
GA
Innovative Power
TM
ActivePMU
TM
-2-
www.active-semi.com
Copyright © 2008 Active-Semi, Inc.
is a trademark of Active-Semi.
ACT6330
ORDERING INFORMATION
PART NUMBER
ACT6330QK-T
Rev0, 02-Apr-08
PACKAGE
TQFN33-16
PINS
16
TEMPERATURE RANGE
-40°C to +85°C
All Active-Semi product are offered in lead-free RoHS Compliant packaging. The term “Pb-free” means semiconductor products that
are in compliance with current RoHS (Restriction of Hazardous Substances) standards.
PIN CONFIGURATION
TOP VIEW
GA
16
GA
GA
GA
FB1
1
2
3
4
5
6
15
ACT6330
EP
7
8
GA
SW1
14
GA
13
12
11
10
9
ON1
ON2
FB2
OVP2
IN
Thin - QFN (TQFN 33-16)
OVP1
SW2
GP12
Innovative Power
TM
ActivePMU
TM
-3-
www.active-semi.com
Copyright © 2008 Active-Semi, Inc.
is a trademark of Active-Semi.
ACT6330
PIN DESCRIPTIONS
PIN
1, 2, 3,
14, 15, 16
4
5
6
7
8
9
10
11
12
13
EP
Rev0, 02-Apr-08
NAME
GA
FB1
OVP1
SW1
GP12
SW2
OVP2
FB2
ON2
ON1
IN
EP
DESCRIPTION
Analog Ground. Connect GAs directly to a quiet ground node. Connect GAs and GP12 to-
gether at a single point as close to the IC as possible.
Feedback Sense for REG1. Connect this pin to the LED string current sense resistor to sense
the LED current.
Over-Voltage Protection Input for REG1. Connect this pin directly to the output node to sense
and prevent over-voltage conditions.
Switching Node Output for REG1. Connect this pin to the switching end of the inductor.
Power Ground for REG1, REG2. Connect GP12 directly to a power ground plane. Connect
GAs and GP12 together at a single point as close to the IC as possible.
Switching Node Output for REG2. Connect this pin to the switching end of the inductor.
Over-Voltage Protection Input for REG2. Connect this pin directly to the output node to sense
and prevent over-voltage conditions.
Feedback Sense for REG2. Connect this pin to the center point of a resistive voltage divider
to sense output voltage.
Enable Control Input for REG2. Drive ON2 to IN or to a logic high for normal operation, drive
to GA or a logic low to disable REG2.
Enable Control Input for REG1. Drive ON1 to IN or to a logic high for normal operation, drive
to GA or a logic low to disable REG1.
Power Input for the IC. Bypass IN to GA with a capacitor placed as close as possible to the IC.
Exposed Pad. Must be soldered to ground on the PCB.
Innovative Power
TM
ActivePMU
TM
-4-
www.active-semi.com
Copyright © 2008 Active-Semi, Inc.
is a trademark of Active-Semi.
ACT6330
ABSOLUTE MAXIMUM RATINGS
PARAMETER
IN, ON1, ON2, FB1, FB2 to GA
OVP1, OVP2, SW1, SW2 to GP12
GP12 to GA
Junction to Ambient Thermal Resistance (θ
JA
)
Operating Temperature Range
Junction Temperature
Store Temperature
Lead Temperature (Soldering, 10 sec)
Rev0, 02-Apr-08
VALUE
-0.3 to +6
-0.3 to +25
-0.3 to +0.3
33.3
-40 to 85
125
-55 to 150
300
UNIT
V
V
V
°C/W
°C
°C
°C
°C
: Do not exceed these limits to prevent damage to the device. Exposure to absolute maximum rating conditions for long periods may
affect device reliability.
Innovative Power
TM
ActivePMU
TM
-5-
www.active-semi.com
Copyright © 2008 Active-Semi, Inc.
is a trademark of Active-Semi.
Embedded System
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