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UPA1725G

Description
Power Field-Effect Transistor, 7A I(D), 20V, 0.03ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, POWER, SOP-8
CategoryDiscrete semiconductor    The transistor   
File Size66KB,8 Pages
ManufacturerNEC Electronics
Download Datasheet Parametric View All

UPA1725G Overview

Power Field-Effect Transistor, 7A I(D), 20V, 0.03ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, POWER, SOP-8

UPA1725G Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerNEC Electronics
Parts packaging codeSOT
package instructionSMALL OUTLINE, R-PDSO-G8
Contacts8
Reach Compliance Codecompliant
ECCN codeEAR99
ConfigurationSINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage20 V
Maximum drain current (ID)7 A
Maximum drain-source on-resistance0.03 Ω
FET technologyMETAL-OXIDE SEMICONDUCTOR
JESD-30 codeR-PDSO-G8
JESD-609 codee0
Number of components1
Number of terminals8
Operating modeENHANCEMENT MODE
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Polarity/channel typeN-CHANNEL
Maximum pulsed drain current (IDM)28 A
Certification statusNot Qualified
surface mountYES
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
transistor applicationsSWITCHING
Transistor component materialsSILICON
Base Number Matches1
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µ
PA1725
SWITCHING
N-CHANNEL POWER MOS FET
INDUSTRIAL USE
DESCRIPTION
This
µ
PA1725 is N-Channel MOS Field Effect Transistor
designed for power management applications of
notebook computers and so on.
8
PACKAGE DRAWING (Unit : mm)
5
1,
2,3
4
5,6,7,8
;
;
;
;
Non connection
Source
Gate
Drain
FEATURES
2.5-V gate drive and low on-resistance
1.8 MAX.
Built-in G-S protection diode
Small and surface mount package (Power SOP8)
0.05 MIN.
Low C
iss
: C
iss
= 950 pF TYP.
0.15
R
DS(on)3
= 30.0 mΩ MAX. (V
GS
= 2.5 V, I
D
= 3.5 A)
+0.10
–0.05
1.44
R
DS(on)1
= 21.0 mΩ MAX. (V
GS
= 4.5 V, I
D
= 3.5 A)
R
DS(on)2
= 22.0 mΩ MAX. (V
GS
= 4.0 V, I
D
= 3.5 A)
1
5.37 MAX.
4
6.0 ±0.3
4.4
0.8
0.5 ±0.2
0.10
1.27 0.78 MAX.
0.40
+0.10
–0.05
0.12 M
ORDERING INFORMATION
PART NUMBER
PACKAGE
Power SOP8
µ
PA1725G
ABSOLUTE MAXIMUM RATINGS (T
A
= 25°C, All terminals are connected.)
Drain to Source Voltage (V
GS
= 0 V)
Gate to Source Voltage (V
DS
= 0 V)
Drain Current (DC)
Drain Current (pulse)
Note1
Note2
V
DSS
V
GSS
I
D(DC)
I
D(pulse)
P
T
T
ch
T
stg
20
±12
±7
±28
2.0
150
–55 to + 150
2
V
V
A
A
W
°C
°C
Gate
Protection
Diode
Source
Gate
Body
Diode
EQUIVALENT CIRCUIT
Drain
Total Power Dissipation (T
A
= 25°C)
Channel Temperature
Storage Temperature
Notes 1.
PW
10
µ
s, Duty Cycle
1 %
2.
Mounted on ceramic substrate of 1200 mm x 2.2mm
Remark
The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage
exceeding the rated voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
G14049EJ1V0DS00 (1st edition)
Date Published January 2000 NS CP(K)
Printed in Japan
The mark
shows major revised points.
©
1999, 2000
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