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CD4508BFMSR

Description
4000/14000/40000 SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, CDIP24, FRIT SEALED, DIP-24
Categorylogic    logic   
File Size88KB,9 Pages
ManufacturerRenesas Electronics Corporation
Websitehttps://www.renesas.com/
Download Datasheet Parametric Compare View All

CD4508BFMSR Overview

4000/14000/40000 SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, CDIP24, FRIT SEALED, DIP-24

CD4508BFMSR Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerRenesas Electronics Corporation
Parts packaging codeDIP
package instructionDIP, DIP24,.6
Contacts24
Reach Compliance Codenot_compliant
series4000/14000/40000
JESD-30 codeR-GDIP-T24
JESD-609 codee0
Load capacitance (CL)50 pF
Logic integrated circuit typeBUS DRIVER
MaximumI(ol)0.00036 A
Number of digits4
Number of functions2
Number of ports2
Number of terminals24
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Output characteristics3-STATE
Output polarityTRUE
Package body materialCERAMIC, GLASS-SEALED
encapsulated codeDIP
Encapsulate equivalent codeDIP24,.6
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5/15 V
Prop。Delay @ Nom-Sup351 ns
propagation delay (tpd)351 ns
Certification statusNot Qualified
Filter levelMIL-PRF-38535 Class V
Maximum seat height5.72 mm
Maximum supply voltage (Vsup)18 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
total dose100k Rad(Si) V
width15.24 mm
Base Number Matches1
CD4508BMS
December 1992
CMOS Dual 4-Bit Latch
Pinout
CD4508BMS
TOP VIEW
RESET A 1
STROBE A 2
OUTPUT DISABLE A 3
D0A 4
Q0A 5
D1A 6
Q1A 7
D2A 8
Q2A 9
D3A 10
24 VDD
23 Q3B
22 D3B
21 Q2B
20 D2B
19 Q1B
18 D1B
17 Q0B
16 D0B
15 OUTPUT DISABLE B
14 STROBE B
13 RESET B
Features
• High-Voltage Types (20-Volt Rating)
• Two Independent 4-Bit Latches
• Individual Master Reset for Each 4-Bit Latch
• 3-State Outputs with High-Impedance State for Bus
Line Applications
• Medium-Speed Operation: tPHL = tPLH = 70nS (Typ.)
at VDD = 10V and CL = 50pF
• 100% Tested for Quiescent Current at 20V
• 5V, 10V, and 15V Parametric Ratings
• Standardized, Symmetrical Output Characteristics
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and 25
o
C
• Noise Margin (Full Package-Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets all Requirements of JEDEC Tentative Standard
No. 13B, "Standard Specifications for Description of
‘B’ Series CMOS Devices"
Q3A 11
VSS 12
Functional Diagram
OUTPUT
DISABLE
D0A
Q0A
4-BIT
LATCH
Q1A
3-STATE
OUTUTS
Q2A
Q3A
Applications
• Buffer Storage
• Holding Registers
• Data Storage and Multiplexing
D1A
D2A
D3A
STROBE
RESET
OUTPUT
DISABLE
D0B
D1B
D2B
D3B
STROBE
RESET
Description
CD4508BMS dual 4-bit latch contains two identical 4-bit
latches with separate STROBE, RESET, and OUTPUT
DISABLE controls. With the STROBE line in the high state,
the data on the "D" inputs appear at the corresponding "Q"
outputs provided the DISABLE line is in the low state.
Changing the STROBE line to the low state locks the data
into the latch. A high on the reset line forces the outputs to a
low level regardless of the state of the STROBE input. The
outputs are forced to the high-impedance state for bus line
applications by a high level on the DISABLE input.
The CD4508BMS is supplied in these 24 lead outline
packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4V
H1Z
H4P
Q0B
Q1B
4-BIT
LATCH
3-STATE
OUTUTS
Q2B
Q3B
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
File Number
3337
7-1148

CD4508BFMSR Related Products

CD4508BFMSR CD4508BKMSR CD4508BDMSR
Description 4000/14000/40000 SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, CDIP24, FRIT SEALED, DIP-24 4000/14000/40000 SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, CDFP24 4000/14000/40000 SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, CDIP24
Is it Rohs certified? incompatible incompatible incompatible
Maker Renesas Electronics Corporation Renesas Electronics Corporation Renesas Electronics Corporation
Parts packaging code DIP DFP DIP
package instruction DIP, DIP24,.6 DFP, FL24,.4 DIP, DIP24,.6
Contacts 24 24 24
Reach Compliance Code not_compliant not_compliant not_compliant
series 4000/14000/40000 4000/14000/40000 4000/14000/40000
JESD-30 code R-GDIP-T24 R-CDFP-F24 R-CDIP-T24
JESD-609 code e0 e0 e0
Load capacitance (CL) 50 pF 50 pF 50 pF
Logic integrated circuit type BUS DRIVER BUS DRIVER BUS DRIVER
MaximumI(ol) 0.00036 A 0.00036 A 0.00036 A
Number of digits 4 4 4
Number of functions 2 2 2
Number of ports 2 2 2
Number of terminals 24 24 24
Maximum operating temperature 125 °C 125 °C 125 °C
Minimum operating temperature -55 °C -55 °C -55 °C
Output characteristics 3-STATE 3-STATE 3-STATE
Output polarity TRUE TRUE TRUE
Package body material CERAMIC, GLASS-SEALED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED
encapsulated code DIP DFP DIP
Encapsulate equivalent code DIP24,.6 FL24,.4 DIP24,.6
Package shape RECTANGULAR RECTANGULAR RECTANGULAR
Package form IN-LINE FLATPACK IN-LINE
Peak Reflow Temperature (Celsius) NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
power supply 5/15 V 5/15 V 5/15 V
Prop。Delay @ Nom-Sup 351 ns 351 ns 351 ns
propagation delay (tpd) 351 ns 351 ns 351 ns
Certification status Not Qualified Not Qualified Not Qualified
Filter level MIL-PRF-38535 Class V MIL-PRF-38535 Class V MIL-PRF-38535 Class V
Maximum seat height 5.72 mm 2.92 mm 5.72 mm
Maximum supply voltage (Vsup) 18 V 18 V 18 V
Minimum supply voltage (Vsup) 3 V 3 V 3 V
Nominal supply voltage (Vsup) 5 V 5 V 5 V
surface mount NO YES NO
technology CMOS CMOS CMOS
Temperature level MILITARY MILITARY MILITARY
Terminal surface Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
Terminal form THROUGH-HOLE FLAT THROUGH-HOLE
Terminal pitch 2.54 mm 1.27 mm 2.54 mm
Terminal location DUAL DUAL DUAL
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
total dose 100k Rad(Si) V 100k Rad(Si) V 100k Rad(Si) V
width 15.24 mm 9.905 mm 15.24 mm

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