Intel
®
Celeron
®
Processor
up to 1.10 GHz
Datasheet
s
s
s
s
s
s
s
Available at 1.10 GHz, 1 GHz, 950 MHz,
900 MHz, 850 MHz, 800 MHz, 766 MHz,
733 MHz, 700 MHz, 667 MHz, 633 MHz,
600 MHz, 566 MHz, 533 MHz,
533A MHz, 500 MHz, 466 MHz,
433 MHz, 400 MHz, 366 MHz, 333 MHz,
and 300A MHz core frequencies with
128 KB level-two cache (on die); 300 MHz
and 266 MHz core frequencies without
level-two cache.
Intel’s latest Celeron
®
processors in the
FC-PGA/FC-PGA2 package are
manufactured using the advanced 0.18
micron technology.
Binary compatible with applications
running on previous members of the Intel
microprocessor line.
Dynamic execution microarchitecture.
Operates on a 100/66 MHz, transaction-
oriented system bus.
Specifically designed for uni-processor
based Value PC systems, with the
capabilities of MMX™ technology.
Power Management capabilities.
s
s
s
s
Optimized for 32-bit applications running
on advanced 32-bit operating systems.
Uses cost-effective packaging technology.
— Single Edge Processor (S.E.P.) Package
to maintain compatibility with SC242
(processor core frequencies (MHz):
266, 300, 300A, 333, 366, 400, 433).
— Plastic Pin Grid Array (PPGA) Package
(processor core frequencies (MHz):
300A, 333, 366, 400, 433, 466, 500,
533).
— Flip-Chip Pin Grid Array (FC-PGA /
FC-PGA2) Package (processor core
frequencies (MHz); 533A, 566, 600,
633, 667, 700, 733, 766, 800, 850, 900,
950); (GHz); 1, 1.10
Integrated high-performance 32 KB
instruction and data, nonblocking, level-
one cache: separate 16 KB instruction and
16 KB data caches.
Integrated thermal diode.
The Intel
®
Celeron
®
processor is designed for uni-processor based Value PC desktops and is
binary compatible with previous generation Intel architecture processors. The Celeron processor
provides good performance for applications running on advanced operating systems such as
Microsoft* Windows*98, Windows NT*, Windows* 2000, Windows XP* and Linux*. This is
achieved by integrating the best attributes of Intel processors—the dynamic execution
performance of the P6 microarchitecture plus the capabilities of MMX™ technology—bringing
a balanced level of performance to the Value PC market segment. The Celeron processor offers
the dependability you would expect from Intel at an exceptional value. Systems based on
Celeron processors also include the latest features to simplify system management and lower the
cost of ownership for small business and home environments.
FC-PGA2 Package
FC-PGA Package
PPGA Package
S.E.P. Package
Document Number:
243658-020
January 2002
Information in this document is provided in connection with Intel
®
products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel
®
Celeron
®
processor may contain design defects or errors known as errata which may cause the product to deviate from published specifi-
cations. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained by calling
1-800-548-4725 or by visiting Intel’s website at http://www.intel.com.
Intel, Celeron, Pentium, MMX and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States
and other countries.
*Other names and brands may be claimed as the property of others.
Copyright
©
1996–2002, Intel Corporation
Datasheet
Intel
®
Celeron
®
Processor up to 1.10 GHz
Contents
1.0
Introduction.......................................................................................................................11
1.1
Terminology.........................................................................................................11
1.1.1 Package Terminology.............................................................................12
1.1.2 Processor Naming Convention...............................................................13
References ..........................................................................................................14
System Bus and Vref...........................................................................................15
Clock Control and Low Power States..................................................................15
2.2.1 Normal State—State 1 ...........................................................................16
2.2.2 AutoHALT Power Down State—State 2 .................................................16
2.2.3 Stop-Grant State—State 3 .....................................................................17
2.2.4 HALT/Grant Snoop State—State 4 ........................................................17
2.2.5 Sleep State—State 5..............................................................................17
2.2.6 Deep Sleep State—State 6 ....................................................................18
2.2.7 Clock Control..........................................................................................18
Power and Ground Pins ......................................................................................18
2.3.1 Phase Lock Loop (PLL) Power...............................................................19
Processor Decoupling .........................................................................................19
2.4.1 System Bus AGTL+ Decoupling.............................................................19
Voltage Identification ...........................................................................................20
System Bus Unused Pins....................................................................................21
Processor System Bus Signal Groups ................................................................21
2.7.1 Asynchronous Vs. Synchronous for System Bus Signals ......................23
2.7.2 System Bus Frequency Select Signal (BSEL[1:0]).................................23
Test Access Port (TAP) Connection....................................................................23
Maximum Ratings................................................................................................23
Processor DC Specifications...............................................................................24
AGTL+ System Bus Specifications .....................................................................33
System Bus AC Specifications ............................................................................34
System Bus Clock (BCLK) Signal Quality Specifications and
Measurement Guidelines ....................................................................................52
AGTL+ Signal Quality Specifications and Measurement Guidelines ..................55
Non-AGTL+ Signal Quality Specifications and Measurement Guidelines...........57
3.3.1 Overshoot/Undershoot Guidelines .........................................................57
3.3.2 Ringback Specification ...........................................................................58
3.3.3 Settling Limit Guideline...........................................................................59
AGTL+ Signal Quality Specifications and Measurement Guidelines
(FC-PGA/FC-PGA2 Packages) ...........................................................................59
3.4.1 Overshoot/Undershoot Guidelines (FC-PGA/FC-PGA2 Packages) .......59
3.4.2 Overshoot/Undershoot Magnitude (FC-PGA/FC-PGA2 Packages) .......59
3.4.3 Overshoot/Undershoot Pulse Duration (FC-PGA/FC-PGA2
Packages) ..............................................................................................60
3.4.4 Activity Factor (FC-PGA/FC-PGA2 Packages) ......................................60
1.2
2.0
2.1
2.2
Electrical Specifications....................................................................................................15
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
3.0
3.1
3.2
3.3
System Bus Signal Simulations........................................................................................52
3.4
Datasheet
3
Intel
®
Celeron
®
Processor up to 1.10 GHz
3.5
4.0
4.1
5.0
Reading Overshoot/Undershoot Specification Tables
(FC-PGA/FC-PGA2 Packages) .............................................................. 61
3.4.6 Determining if a System meets the Overshoot/Undershoot
Specifications (FC-PGA/FC-PGA2 Packages)....................................... 62
Non-AGTL+ Signal Quality Specifications and Measurement Guidelines........... 64
Thermal Specifications........................................................................................ 65
4.1.1 Thermal Diode........................................................................................ 68
S.E.P. Package ................................................................................................... 69
5.1.1 Materials Information.............................................................................. 69
5.1.2
Signal Listing (S.E.P. Package) ............................................................ 70
PPGA Package ................................................................................................... 79
5.2.1 PPGA Package Materials Information.................................................... 79
5.2.2 PPGA Package Signal Listing ................................................................ 81
FC-PGA/FC-PGA2 Packages ............................................................................. 92
5.3.1 FC-PGA Mechanical Specifications ....................................................... 92
5.3.2 Mechanical Specifications (FC-PGA2 Package) .................................... 94
5.3.2.1 Recommended Mechanical Keep-Out Zones
(FC-PGA2 Package) ................................................................. 96
5.3.3 FC-PGA/FC-PGA2 Package Signal List................................................. 97
Processor Markings (PPGA/FC-PGA/FC-PGA2 Packages) ............................. 108
Heatsink Volumetric Keepout Zone Guidelines................................................. 109
Mechanical Specifications for the Boxed Intel
®
Celeron
®
Processor ................ 110
6.1.1 Mechanical Specifications for the S.E.P. Package............................... 110
6.1.1.1 Boxed Processor Heatsink Weight.......................................... 112
6.1.1.2 Boxed Processor Retention Mechanism ................................. 112
6.1.2 Mechanical Specifications for the PPGA Package............................... 113
6.1.2.1 Boxed Processor Heatsink Weight.......................................... 114
6.1.3 Mechanical Specifications for the FC-PGA/FC-PGA2 Packages......... 114
6.1.3.1 Boxed Processor Heatsink Weight.......................................... 115
Thermal Specifications...................................................................................... 115
6.2.1 Thermal Requirements for the Boxed Intel
®
Celeron
®
Processor........ 115
6.2.1.1 Boxed Processor Cooling Requirements ................................ 115
6.2.1.2 Boxed Processor Thermal Cooling Solution Clip .................... 117
Electrical Requirements for the Boxed Intel
®
Celeron
®
Processor ................... 117
6.3.1 Electrical Requirements ....................................................................... 117
Signal Summaries ............................................................................................. 126
3.4.5
Thermal Specifications and Design Considerations......................................................... 65
Mechanical Specifications................................................................................................ 69
5.1
5.2
5.3
5.4
5.5
6.0
6.1
Boxed Processor Specifications..................................................................................... 110
6.2
6.3
7.0
Processor Signal Description ......................................................................................... 120
7.1
4
Datasheet
Intel
®
Celeron
®
Processor up to 1.10 GHz
Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Clock Control State Machine...............................................................................16
BCLK to Core Logic Offset ..................................................................................48
BCLK*, PICCLK, and TCK Generic Clock Waveform .........................................49
System Bus Valid Delay Timings ........................................................................49
System Bus Setup and Hold Timings..................................................................49
System Bus Reset and Configuration Timings (For the S.E.P. and
PPGA Packages) ................................................................................................50
System Bus Reset and Configuration Timings (For the
FC-PGA/FC-PGA2 Package) ..............................................................................50
Power-On Reset and Configuration Timings.......................................................51
Test Timings (TAP Connection) ..........................................................................51
Test Reset Timings .............................................................................................51
BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Core Pins .....53
BCLK, TCK, PICCLK Generic Clock Waveform at the Processor
Edge Fingers .......................................................................................................54
Low to High AGTL+ Receiver Ringback Tolerance.............................................56
Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback .....................57
Maximum Acceptable AGTL+ Overshoot/Undershoot Waveform
(FC-PGA/FC-PGA2 Packages) ...........................................................................63
Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback ....................64
Processor Functional Die Layout (CPUID 0686h)...............................................67
Processor Functional Die Layout (up to CPUID 0683h)......................................67
Processor Substrate Dimensions (S.E.P. Package) ...........................................70
Processor Substrate Primary/Secondary Side Dimensions (S.E.P. Package)....70
Package Dimensions (PPGA Package) ..............................................................79
PPGA Package (Pin Side View)..........................................................................81
Package Dimensions (FC-PGA Package)...........................................................92
Package Dimensions (FC-PGA2 Package).........................................................94
Volumetric Keep-Out ...........................................................................................96
Component Keep-Out .........................................................................................96
Package Dimensions (FC-PGA/FC-PGA2 Packages) ........................................97
Top Side Processor Markings (PPGA Package)...............................................108
Top Side Processor Markings (FC-PGA Package) ...........................................108
Top Side Processor Markings (FC-PGA2 Package) .........................................108
Retention Mechanism for the Boxed Intel® Celeron
®
Processor in the
S.E.P. Package .................................................................................................111
Side View Space Requirements for the Boxed Processor in the S.E.P.
Package ............................................................................................................111
Front View Space Requirements for the Boxed Processor in the S.E.P.
Package ............................................................................................................112
Boxed Intel
®
Celeron
®
Processor in the PPGA Package..................................113
Side View Space Requirements for the Boxed Processor in the PPGA
Package ............................................................................................................113
Conceptual Drawing of the Boxed Intel
®
Celeron
®
Processor in the
370-Pin Socket (FC-PGA/FC-PGA2 Packages)................................................114
Dimensions of Mechanical Step Feature in Heatsink Base for the
FC-PGA/FC-PGA2 Packages ...........................................................................114
Top View Airspace Requirements for the Boxed Processor in the
S.E.P. Package .................................................................................................115
Datasheet
5
京公网安备 11010802033920号
EEWORLD
