MC9S08MP16E2VLF datasheet, PDF

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MC9S08MP16E2VLF: Description8-BIT, FLASH, 50.33 MHz, MICROCONTROLLER, PQFP48; Categorysemiconductor The embedded processor and controller; File Size419KB，36 Pages; ManufacturerFREESCALE (NXP)

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MC9S08MP16E2VLF Overview

8-BIT, FLASH, 50.33 MHz, MICROCONTROLLER, PQFP48

MC9S08MP16E2VLF Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	48
Maximum operating temperature	125 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	5.5 V
Minimum supply/operating voltage	2.7 V
Rated supply voltage	5 V
External data bus width	0.0
Line speed	50.33 MHz
Processing package description	Square flat package-48
Lead-free	Yes
EU RoHS regulations	Yes
state	ACTIVE
packaging shape	SQUARE
Package Size	FLATPACK, LOW PROFILE, FINE PITCH
surface mount	Yes
Terminal form	GULL WING
Terminal spacing	0.5000 mm
terminal coating	NOT SPECIFIED
Terminal location	Four
Packaging Materials	Plastic/Epoxy
Temperature level	AUTOMOTIVE
ADC channel	Yes
Address bus width	0.0
Number of digits	8
Maximum FCLK clock frequency	16 MHz
DAC channel	Yes
Microprocessor type	Microcontroller
PWM channel	Yes
ROM programming	FLASH

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Freescale Semiconductor

Data Sheet: Technical Data

Document Number: MC9S08MP16

Rev. 1, 10/2009

MC9S08MP16 Series Data

Sheet

Features

• 8-Bit HCS08 Central Processor Unit (CPU)

– Up to 51.34 MHz CPU at 2.7V to 5.5V across temperature

range of –40°C to 105°C

– Up to 40 MHz CPU at 2.7V to 5.5V across temperature range

of –40°C to 125°C

– HC08 instruction set with added BGND instruction and

additional addressing modes for LDHX and STHX

– Support for up to 48 interrupt/reset sources

• On-Chip Memory

– Up to 16 KB flash memory; read/program/erase over full

operating voltage and temperature

– Up to 1 KB random-access memory (RAM)

– Security circuitry to prevent unauthorized access to RAM and

flash memory contents

• Power-Saving Modes

– Two low power stop modes; reduced power wait mode

– Peripheral clock gating can disable clocks to unused modules

• Clock Source Options

– Oscillator (XOSC) — Loop-control Pierce oscillator; Crystal

or ceramic resonator range of 31.25–38.4 kHz or 1–16 MHz

– Internal Clock Source (ICS) — Containing a

frequency-locked-loop (FLL) controlled by internal or

external reference; precision trimming of internal reference

allows 0.2% resolutions and 2% deviation over temperature

and voltage; supports CPU frequencies up to 51.34 MHz

• System Protection

– Watchdog computer operating properly (COP) reset running

from dedicated 1-kHz internal clock source or bus clock

– Low-voltage detection with reset or interrupt; selectable trip

points

– Illegal opcode and illegal address detection with reset

– Flash memory block protection

• Development Support

– Single-wire background debug interface

– Breakpoint capability to allow single breakpoint setting during

in-circuit debugging (plus three more breakpoints in on-chip

debug module)

– On-chip in-circuit emulator (ICE) debug module containing

three comparators and nine trigger modes. Eight deep FIFO for

storing change-of-flow addresses and event-only data. Debug

module supports both tag and force breakpoints

• Peripherals

–

IPC

— Interrupt Priority Controller with 4 programmable

interrupt priority levels

–

ADC

— 13-channel, 12-bit resolution; 2.5

μs

conversion time;

automatic compare function; 1.7 mV/°C temperature sensor;

internal bandgap reference channel; operation in stop3

48-LQFP

Case 932-03

28-SOIC

Case 751F-05

32-LQFP

Case 873A-03

–

PGA

— Differential programmable gain amplifier with

programmable gain (x1, x2, x4, x8, x16, or x32)

–

HSCMP

— Three fast analog comparators with positive and

negative inputs; separately selectable interrupt on rising and

falling comparator output; filtering; windowing; HSCMP1 and

HSCMP2 outputs can be optionally routed to FTM1 module;

runs in stop3

–

DAC

— Three 5-bit digital to analog convertor used as a

32-tap voltage reference for each comparator

–

PDB

— Two programmable delay blocks: PDB1 synchronizes

PWM with samples of ADC; PDB2 synchronizes PWM with

comparing window of analog comparators

–

SCI

— Full duplex non-return to zero (NRZ); LIN master

extended break generation; LIN slave extended break

detection; wake up on active edge

–

SPI

— Full-duplex or single-wire bidirectional;

Double-buffered transmit and receive; Master or Slave mode;

MSB-first or LSB-first shifting

–

IIC/SMBus

— Up to 400 kbps; Multi-master operation;

Programmable slave address; Interrupt driven byte-by-byte

data transfer; supports broadcast mode and 10-bit addressing;

SMBus compatible

–

FTM

— Two Flextimers with total of 8 channels; One

2-channel (FTM1) and one 6-channel (FTM2); supports

operation up to 2x bus clock; selectable input capture, output

compare, edge- or center-aligned PWM; dead time insertion;

fault inputs

–

MTIM

— 8-bit modulo counter with 8-bit prescaler

–

RTC

— (Real-time counter) 8-bit modulus counter with

binary or decimal based prescaler; External clock source for

precise time base, time-of-day, calendar or task scheduling;

Free running on-chip low power oscillator (1 kHz) for cyclic

wake-up without external components, runs in all MCU modes

–

CRC

— Cyclic redundancy check generator

–

KBI

— Three 8 channel keyboard interrupt module with

software selectable polarity on edge or edge/level modes

• Input/Output

– 40 GPIOs, 2 output-only pins.

– Hysteresis and configurable pull up device on input pins;

Configurable slew rate and drive strength on output pins;

Sink/Source current up to 20mA

• Package Options

– 48-LQFP, 32-LQFP, 28-SOIC

– 48-LQFP qualified for automotive usage

Freescale reserves the right to change the detail specifications as may be required to permit

improvements in the design of its products.

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