19-4994; Rev 0; 10/09
KIT
ATION
EVALU
E
BL
AVAILA
76V, APD, Bias Output Stage with
Current Monitoring
General Description
Features
♦
76V Maximum Boost Voltage
♦
Switch FET
♦
Current Monitor with a Wide 1µA to 2mA Range,
Fast 50ns Time Constant, and 10:1 and 5:1 Ratio
♦
2mA Current Clamp with External Shutdown
♦
Precision Voltage Feedback
♦
Multiple External Filtering Options
♦
3mm x 3mm, 14-Pin TDFN Package with Exposed Pad
DS1842A
The DS1842A integrates the discrete high-voltage
components necessary for avalanche photodiode
(APD) bias and monitor applications. A switch FET and
precision voltage-divider network are used in conjunc-
tion with an external DC-DC controller to create a boost
DC-DC converter. A current clamp limits current
through the APD and also features an external shut-
down. The precision voltage-divider network is provid-
ed for precise control of the APD bias voltage. The
device also includes a dual current mirror to monitor
the APD current.
Applications
APD Biasing
GPON ONU and OLT
PART
DS1842AN+
DS1842AN+T&R
Ordering Information
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
14 TDFN-EP*
14 TDFN-EP*
+Denotes
a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
*EP
= Exposed pad.
Typical Application Circuit
3.3V
LX
FBIN
C
BULK
DS1842A
SW
GATE
PGND
FBOUT
R
2
C
COMP
R
COMP
COMP
D2
CLAMP
CURRENT
LIMIT
MIROUT
ROSA
MIR1
R
1
MIRIN
CURRENT MIRROR
FB
MIR2
EXTERNAL MONITOR
EP GND
DS1875
APD
TIA
MON3
NOTE:
SEE THE
LAYOUT CONSIDERATIONS
SECTION.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
76V, APD, Bias Output Stage with
Current Monitoring
DS1842A
ABSOLUTE MAXIMUM RATINGS
Voltage Range on GATE and CLAMP
Relative to GND...................................................-0.3V to +12V
Voltage Range on MIRIN, MIROUT, FBIN
MIR1, and MIR2 Relative to GND........................-0.3V to +80V
Voltage Range on FBOUT Relative to GND ..........-0.3V to +6.0V
Voltage Range on LX Relative to GND...................-0.3V to +85V
Operating Junction Temperature Range ...........-40°C to +150°C
Storage Temperature Range .............................-55°C to +135°C
Soldering Temperature ..........................Refer to the IPC JEDEC
J-STD-020 Specification.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(T
A
= -40°C to +85°C, unless otherwise noted.)
PARAMETER
Switching Frequency
FET Capacitance
FET Gate Resistance
FET On-Resistance
GATE Voltage
Switching Current
LX Voltage
LX Leakage
CLAMP Voltage
CLAMP Threshold
Maximum MIROUT Current
MIR1 to MIROUT Ratio
MIR2 to MIROUT Ratio
MIR1, MIR2 Rise Time
(20%/80%)
Shutdown Temperature
Hysteresis Temperature
Leakage on GATE and CLAMP
Resistor-Divider Ratio (R
1
/R
2
)
Resistor-Divider Tempco
Resistor-Divider End-to-End
Resistance
R
RES
T
A
= +25°C, V
FBIN
= 76V
308
SYMBOL
f
SW
C
GATE
C
LX
R
G
R
DSON
V
GS
I
LX
V
LX
I
IL(LX)
V
CLAMP
V
CLT
I
MIROUT
K
MIR1
K
MIR2
t
RC
T
SHDN
T
HYS
I
IL
K
R
T
A
= +25°C, V
FBIN
= 76V
CLAMP = low
CLAMP = high
15V < V
MIRIN
< 76V, I
MIROUT
> 1μA
15V < V
MIRIN
< 76V, I
MIROUT
> 1μA
(Note 1)
(Note 2)
(Note 2)
-1
59.5
±50
385
481
0.096
0.192
0.100
0.200
30
+150
5
+1
60.25
ppm/°C
k
V
GATE
= 0V, V
LX
= 76V
-1
0
1.25
1.8
1.8
2.75
Duty cycle = 10%, f
SW
= 100kHz
V
GS
= 3V, I
D
= 170mA
V
GS
= 10V, I
D
= 170mA
0
V
GS
= 0V, V
DS
= 25V
f
SW
= 1MHz
CONDITIONS
MIN
0
40
90
22
1
0.75
2
1.4
11
680
80
+1
11
2.35
3.85
10
0.104
0.208
V
mA
V
μA
V
V
mA
μA
A/A
A/A
ns
°C
°C
μA
TYP
MAX
1.2
UNITS
MHz
pF
Note 1:
Rising MIROUT transition from 10µA to 1mA; V
MIRIN
= 40V, 2.5kΩ load.
Note 2:
Not production tested. Guaranteed by design.
2
_______________________________________________________________________________________
76V, APD, Bias Output Stage with
Current Monitoring
Typical Operating Characteristics
(T
A
= +25°C, unless otherwise noted.)
MIRIN CURRENT vs. MIROUT CURRENT
(V
MIRIN
= 40V)
DS1842A toc01
DS1842A
MIRIN CURRENT vs. TEMPERATURE
(V
MIRIN
= 40V, I
MIROUT
= 250nA)
90
80
MIRIN CURRENT (μA)
70
60
50
40
30
20
10
DS1842A toc02
10,000
100
MIRIN CURRENT (μA)
1000
100
10
1
10
100
1000
10,000
MIROUT CURRENT (μA)
0
-40
-20
0
20
40
60
80
100
TEMPERATURE (°C)
MIRIN CURRENT vs. TEMPERATURE
(V
MIRIN
= 40V, I
MIROUT
= 2mA)
DS1842A toc03
MIR ERROR vs. TEMPERATURE
(I
MIROUT
= 1μA)
V
MIRIN
= 40V
1
ERROR (%)
DS1842A toc04
5
2
4
MIRIN CURRENT (mA)
MIR2
3
0
MIR1
-1
2
1
0
-40
-20
0
20
40
60
80
100
TEMPERATURE (°C)
-2
-40
-20
0
20
40
60
80
100
TEMPERATURE (°C)
MIR ERROR vs. TEMPERATURE
(I
MIROUT
= 1mA)
V
MIRIN
= 40V
1
ERROR (%)
ERROR (%)
DS1842A toc05
MIR ERROR vs. MIROUT CURRENT
V
MIRIN
= 40V
1
DS1842A toc06
2
2
0
0
MIR2
MIR1
MIR2
MIR1
-1
-1
-2
-40
-20
0
20
40
60
80
100
TEMPERATURE (°C)
-2
1
10
100
1000
10,000
MIROUT CURRENT (μA)
_______________________________________________________________________________________
3
76V, APD, Bias Output Stage with
Current Monitoring
DS1842A
Typical Operating Characteristics (continued)
(T
A
= +25°C, unless otherwise noted.)
MIR ERROR
vs. MIRIN VOLTAGE
DS1842A toc07
MIROUT CLAMP CURRENT
vs. MIRIN VOLTAGE
3.4
3.3
3.2
I
MIROUT
(mA)
3.1
3.0
2.9
2.8
2.7
2.6
T
A
= +85°C
T
A
= +25°C
T
A
= -40°C
DS1842A toc08
2
3.5
1
ERROR (%)
I
MIR2
= 1μA
I
MIR2
= 1mA
0
I
MIR1
= 1μA
I
MIR1
= 1mA
-1
-2
10
20
30
40
50
60
70
80
MIRIN VOLTAGE (V)
2.5
10
20
30
40
50
60
70
80
MIRIN VOLTAGE (V)
FET ON-RESISTANCE
vs. DRAIN CURRENT
DS1842A toc09
FET ON-RESISTANCE
vs. TEMPERATURE
I
D
= 170mA
V
GS
= 2.5V
1.5
V
GS
= 3.0V
V
GS
= 3.6V
DS1842A toc10
2.0
V
GS
= 2.5V
1.5
R
DSON
(Ω)
2.0
1.0
R
DSON
(Ω)
1.0
V
GS
= 5.0V
0.5
V
GS
= 3.0V
V
GS
= 3.6V
V
GS
= 5V
V
GS
= 10V
0.5
100
I
DS
(mA)
1000
-40
-20
0
20
40
V
GS
= 10V
60
80
100
0
1
10
TEMPERATURE (°C)
RESISTOR-DIVIDER RATIO
vs. FBIN VOLTAGE
DS1842A toc11
RESISTOR-DIVIDER RATIO
vs. TEMPERATURE
V
FBIN
= 40V
DS1842A toc12
60.1
60.00
60.0
RATIO (K
R
)
59.95
RATIO (K
R
)
10
20
30
40
50
60
70
80
59.9
59.90
59.8
59.85
59.7
FBIN VOLTAGE (V)
59.80
-40
-20
0
20
40
60
80
100
TEMPERATURE (°C)
4
_______________________________________________________________________________________
76V, APD, Bias Output Stage with
Current Monitoring
Pin Configuration
TOP VIEW
DS1842A
MIR1
MIR2
GND
FBOUT
CLAMP
GATE
PGND
1
2
3
4
5
6
*EP
7
8
LX
DS1842A
14 MIROUT
13 MIRIN
12 FBIN
GATE
11 N.C.
10 N.C.
9
N.C.
CLAMP
PGND
CURRENT
LIMIT
THERMAL
SHUTDOWN
MIR1
MIR2
FBOUT
LX
R
2
CURRENT MIRROR
R
1
FBIN
MIRIN
Block Diagram
DS1842A
+
TDFN
*EXPOSED PAD.
EP
GND
MIROUT
Pin Description
PIN
1
2
3
4
5
6
7
8
9, 10, 11
12
13
14
—
NAME
MIR1
MIR2
GND
FBOUT
CLAMP
GATE
PGND
LX
N.C.
FBIN
MIRIN
MIROUT
EP
Current Mirror Monitor Output, 10:1 Ratio
Current Mirror Monitor Output, 5:1 Ratio
Ground Connection for Device. Connect directly to ground plane. Connect GND to PGND at a
single point. See the
Layout Considerations
section for more information.
Feedback Output. Resistor-divider output.
Clamp Input. Disables the current mirror output (MIROUT).
FET Gate Connection
Source of Switch FET. Also connect to boost converter’s input and output capacitors. Connect
PGND to GND at a single point. See the
Layout Considerations
section for more information.
FET Drain Connection. Connect to switching inductor.
No Connection
Feedback Input. Resistor-divider input.
Current Mirror Input
Current Mirror Output. Connect to APD bias pin.
Exposed Pad. Connect directly to the same ground plane as GND.
FUNCTION
Detailed Description
The DS1842A contains discrete high-voltage compo-
nents required to create an APD bias voltage and to
monitor the APD bias current. The device’s mirror out-
puts are a current that is a precise ratio of the output
current across a large dynamic range. The mirror
response time is fast enough to comply with GPON Rx
burst-mode monitoring requirements. The device has a
built-in current-limiting feature to protect APDs. The
APD current can also be shut down by CLAMP or ther-
mal shutdown. The internal FET and resistor-divider are
used in conjunction with a DC-DC boost controller to
precisely create the APD bias voltage.
Current Mirror
The DS1842A has two current mirror outputs. One is a
10:1 mirror connected at MIR1, and the other is a 5:1
mirror connected to MIR2.
5
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