K6T4016S3C Family
Document Title
256Kx16 bit Low Power and Low Voltage CMOS Static RAM
CMOS SRAM
Revision History
Revision No. History
0.0
0.01
1.0
Initial draft
Errata correction
Finalize
Draft Date
June 16, 1998
August 10, 1998
April 30, 1999
Remark
Preliminary
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will anwswer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 1.0
April 1999
K6T4016S3C Family
256Kx16 bit Low Power and Low Voltage CMOS Static RAM
FEATURES
•
Process Technology: TFT
•
Organization: 256K x16
•
Power Supply Voltage: 2.3~2.7V
•
Low Data Retention Voltage: 2V(Min)
•
Three state output and TTL Compatible
•
Package Type: 44-TSOP2-400F/R
CMOS SRAM
GENERAL DESCRIPTION
The K6T4016S3C families are fabricated by SAMSUNG′s
advanced CMOS process technology. The families support
industrial operating temperature ranges and have small pack-
age types for user flexibility of system design. The families also
support low data retention voltage for battery back-up operation
with low data retention current.
PRODUCT FAMILY
Power Dissipation
Product Family
K6T4016S3C-F
Operating Temperature
Industrial(-40~85°C)
Vcc Range
2.3~2.7V
Speed
100
1)
/120ns
Standby
(I
SB1
, Max)
15µA
Operating
(I
CC2
, Max)
25mA
PKG Type
44-TSOP2-F/R
1. The parameter is measured with 30pF test load.
PIN DESCRIPTION
A4
A3
A2
A1
A0
CS
I/OI
I/O2
I/O3
I/O4
Vcc
Vss
I/O5
I/O6
I/O7
I/O8
WE
A17
A16
A15
A14
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
Vss
Vcc
I/O12
I/O11
I/O10
I/O9
N.C
A8
A9
A10
A11
A12
A5
A6
A7
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
Vss
Vcc
I/O12
I/O11
I/O10
I/O9
N.C
A8
A9
A10
A11
A12
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A4
A3
A2
A1
A0
CS
I/OI
I/O2
I/O3
I/O4
Vcc
Vss
I/O5
I/O6
I/O7
I/O8
WE
A17
A16
A15
A14
A13
FUNCTIONAL BLOCK DIAGRAM
Clk gen.
A0
A1
A2
A3
A4
A13
A14
A15
A16
A17
I/O
1
~I/O
8
Precharge circuit.
Vcc
Vss
44-TSOP2
Forward
44-TSOP2
Reverse
Row
selec
Memory array
1024 rows
256×16 columns
Data
cont
Data
cont
Data
cont
I/O Circuit
Column select
I/O
9
~I/O
16
Name
CS
OE
WE
A
0
~A
17
Function
Chip Select Input
Output Enable Input
Write Enable Input
Address Inputs
Name Function
Vcc
Vss
UB
LB
N.C
Power
Ground
Upper Byte(I/O
9~16
)
Lower Byte (I/O
1~8
)
No Connection
WE
OE
UB
LB
CS
A5 A6 A7 A8 A9 A10 A11 A12
Control
logic
I/O
1
~I/O
16
Data Input/Output
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice.
2
Revision 1.0
April 1999
K6T4016S3C Family
PRODUCT LIST
Industrial Temperature Products(-40~85°C)
Part Name
K6T4016S3C-TF10
K6T4016S3C-TF12
K6T4016S3C-RF10
K6T4016S3C-RF12
Function
CMOS SRAM
44-TSOP2-F, 100ns, 2.5V, LL
44-TSOP2-F, 120ns, 2.5V, LL
44-TSOP2-R, 100ns, 2.5V, LL
44-TSOP2-R, 120ns, 2.5V, LL
FUNCTIONAL DESCRIPTION
CS
H
L
L
L
L
L
L
L
L
OE
X
1)
H
X
1)
L
L
L
X
1)
X
1)
X
1)
WE
X
1)
H
X
1)
H
H
H
L
L
L
LB
X
1)
X
1)
H
L
H
L
L
H
L
UB
X
1)
X
1)
H
H
L
L
H
L
L
I/O
1~8
High-Z
High-Z
High-Z
Dout
High-Z
Dout
Din
High-Z
Din
I/O
9~16
High-Z
High-Z
High-Z
High-Z
Dout
Dout
High-Z
Din
Din
Mode
Deselected
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
Lower Byte Write
Upper Byte Write
Word Write
Power
Standby
Active
Active
Active
Active
Active
Active
Active
Active
1. X means don′t care. (Must be in low or high state)
ABSOLUTE MAXIMUM RATINGS
1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Storage temperature
Operating Temperature
Symbol
V
IN
,V
OUT
V
CC
P
D
T
STG
T
A
Ratings
-0.5 to V
CC
+0.5
-0.3 to 4.6
1.0
-65 to 150
-40 to 85
Unit
V
V
W
°C
°C
Remark
-
-
-
-
Industrial Product
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 1.0
April 1999
K6T4016S3C Family
RECOMMENDED DC OPERATING CONDITIONS
1)
Item
Supply voltage
Ground
Input high voltage
Input low voltage
Symbol
Vcc
Vss
V
IH
V
IL
Product
K6T4016S3C Family
All Family
All Family
All Family
Min
2.3
0
2.0
-0.3
3)
Typ
2.5
0
-
-
CMOS SRAM
Max
2.7
0
Vcc+0.3
2)
0.6
Unit
V
V
V
V
Note:
1. T
A
=-40 to 85°C, otherwise specified
2. Overshoot : V
CC
+1.0V in case of pulse width
≤
20ns
3. Undershoot : -1.0V in case of pulse width
≤
20ns
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE
1)
(f=1MHz, T
A
=25°C)
Item
Input capacitance
Input/Output capacitance
1. Capacitance is sampled, not 100% tested
Symbol
C
IN
C
IO
Test Condition
V
IN
=0V
V
IO
=0V
Min
-
-
Max
8
10
Unit
pF
pF
DC AND OPERATING CHARACTERISTICS
Item
Input leakage current
Output leakage current
Operating power supply current
Average operating current
Output low voltage
Output high voltage
Standby Current(TTL)
Standby Current(CMOS)
Symbol
I
LI
I
LO
I
CC
I
CC1
I
CC2
V
OL
V
OH
I
SB
I
SB1
V
IL
=Vss to Vcc
CS=V
IH
or OE=V
IH
or WE=V
IL
V
IO
=Vss to Vcc
I
IO
=0mA, CS=V
IL
, V
IN
=V
IL
or V
IH
, Read
Cycle time=1µs, 100% duty, I
IO
=0mA, CS≤0.2V, V
IN
≤0.2V
or V
IN
≥Vcc-0.2V
Test Conditions
Min
-1
-1
-
-
-
-
2.0
-
-
Typ
-
-
-
-
-
-
-
-
-
Max
1
1
1
4
25
0.4
-
0.3
15
Unit
µA
µA
mA
mA
mA
V
V
mA
µA
Cycle time=Min, 100% duty, I
IO
=0mA, CS=V
IL
, V
IN
=V
IH
or V
IL
I
OL
=0.5mA
I
OH
=-0.5mA
CS=V
IH
, Other inputs = V
IL
or V
IH
CS≥Vcc-0.2V, Other inputs=0~Vcc
4
Revision 1.0
April 1999
K6T4016S3C Family
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage: 1.1V
Output load(see right): C
L
=100pF+1TTL
C
L
=30pF+1TTL
CMOS SRAM
C
L
1
)
1.Including scope and jig capacitance
AC CHARACTERISTICS
(V
CC
=2.3~2.7V, T
A
=-40 to 85°C)
Speed Bins
Parameter List
Symbol
100ns
Min
Read cycle time
Address access time
Chip select to output
Output enable to valid output
LB, UB valid to data output
Read
Chip select to low-Z output
Output enable to low-Z output
LB, UB enable to low-Z output
Output hold from address change
Chip disable to high-Z output
OE disable to high-Z output
UB, LB disable to high-Z output
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
Write pulse width
Write
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
LB, UB valid to end of write
t
RC
t
AA
t
CO
t
OE
t
BA
t
LZ
t
OLZ
t
BLZ
t
OH
t
HZ
t
OHZ
t
BHZ
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
t
BW
100
-
-
-
-
10
5
5
15
0
0
0
100
80
0
80
70
0
0
40
0
5
80
Max
-
100
100
50
50
-
-
-
-
30
30
30
-
-
-
-
-
-
30
-
-
-
-
Min
120
-
-
-
-
10
5
5
15
0
0
0
120
100
0
100
80
0
0
50
0
5
100
120ns
Max
-
120
120
60
60
-
-
-
-
35
35
35
-
-
-
-
-
-
35
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
Symbol
V
DR
I
DR
t
SDR
t
RDR
Test Condition
CS≥Vcc-0.2V
Vcc=2.5V, CS≥Vcc-0.2V
See data retention waveform
Min
2.0
-
0
5
Typ
-
0.5
-
-
Max
2.7
15
-
-
Unit
V
µA
ms
5
Revision 1.0
April 1999