the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FS
L
C is a three-level input. Please see the V
IL_FS
and V
IH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
PCI0/CR#_A
VDDPCI
PCI4/SRC5_EN
PCI_F5/ITP_EN
GNDPCI
VDD48
USB_48MHz/FSLA
GND48
VDD96_IO
DOT96T_LPR/SRCT0_LPR
DOT96C_LPR/SRCC0_LPR
GND
VDD
SE1
GND
SRCT2_LPR/SATAT_LPR
SRCC2_LPR/SATAC_LPR
GNDSRC
SRCT3_LPR/CR#_C
SRCC3_LPR/CR#_D
VDDSRC_IO
SRCT4_LPR
SRCC4_LPR
CPU_STOP#/SRCC5_LPR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SCLK
SDATA
REF0/FSLC/TEST_SEL
VDDREF
X1
X2
GNDREF
FSLB/TEST_MODE
CK_PWRGD/PD#
VDDCPU
CPUT0_LPR
CPUC0_LPR
GNDCPU
CPUT1_LPR_F
CPUC1_LPR_F
VDDCPU_IO
CPUT2_ITP_LPR/SRCT8_LPR
CPUC2_ITP_LPR/SRCC8_LPR
VDDSRC_IO
SRCT7_LPR/CR#_F
SRCC7_LPR/CR#_E
GNDSRC
VDDSRC
PCI_STOP#/SRCT5_LPR
48-SSOP/TSSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
1461A—07/28/09
ADVANCE INFORMATION
documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
9LPRS535
Integrated
Circuit
Systems, Inc.
ICS9LPRS535
Datasheet
SSOP/TSSOP Pin Description
PIN #
1
2
3
PIN NAME
PCI0/CR#_A
VDDPCI
PCI4/SRC5_EN
TYPE
DESCRIPTION
4
5
6
7
8
9
10
PCI_F5/ITP_EN
GNDPCI
VDD48
USB_48MHz/FSLA
GND48
VDD96_IO
DOT96T_LPR/SRCT0_LPR
3.3V PCI clock output or CR#_A input. Default is PCI0. To configure this pin as CR#_A, the PCI output must first be disabled in
OUT True clock of push-pull SRC output with int. 33ohm series resistor.
OUT Complementary clock of push-pull SRC output with int. 33ohm series resistor.
I/O
Stops all CPUCLK, except those set to be free running clocks /
Complementary clock of push-pull SRC pair with int. 33ohm series resistor.
11
12
13
14
15
16
17
18
19
DOT96C_LPR/SRCC0_LPR
GND
VDD
SE1
GND
SRCT2_LPR/SATAT_LPR
SRCC2_LPR/SATAC_LPR
GNDSRC
SRCT3_LPR/CR#_C
20
21
22
23
24
SRCC3_LPR/CR#_D
VDDSRC_IO
SRCT4_LPR
SRCC4_LPR
CPU_STOP#/SRCC5_LPR
1461A—07/28/09
2
Integrated
Circuit
Systems, Inc.
ICS9LPRS535
Datasheet
SSOP/TSSOP Pin Description (Continued)
25
26
27
28
PCI_STOP#/SRCT5_LPR
VDDSRC
GNDSRC
I/O
Stops all PCICLKs at logic 0 level, when low. Can also stop SRC clocks. Free running PCICLKs are not effected by this
input. / True clock of push-pull SRC pair with int. 33ohm series resistor.
PWR Supply for SRC clocks, 3.3V nominal
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
PWR Ground pin for the SRC outputs
Complementary clock of push-pull SRC output with int. 33ohm series resistor/CR#_E input. Disable SRC7 via Byte 3, bit 3
before using as CR#_E.
SRCC7_LPR/CR#_E
I/O
Byte 6, bit 7: 0=SRC7 (default), 1=CR#_E
Outputs controlled by CR#_E are not present on this device
True clock of push-pull SRC output with int. 33 ohm series resistor/CR#_F input. Disable SRC7 via Byte 3, bit 3 before
SRCT7_LPR/CR#_F
I/O using CR#_F.
Byte 6, bit 6: 0 = SRC7 (default),1 = CR#_F enabled to control SRC8.
VDDSRC_IO
PWR 1.05V to 3.3V from external power supply
Complementary clock of low power differential CPU2_ITP/SRC pair. No Rs needed. The function of this pin is determined
by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows:
CPUC2_ITP_LPR/SRCC8_LPR OUT Pin 7 latched input Value
0 = SRC8#
1 = ITP#
True clock of low power differential CPU2_ITP/SRC8 pair. No Rs needed. The function of this pin is determined by the
latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows:
CPUT2_ITP_LPR/SRCT8_LPR OUT Pin 7 latched input Value
0 = SRC8
1 = ITP
VDDCPU_IO
PWR 1.05V to 3.3V from external power supply
Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm series resistor. Free running
CPUC1_LPR_F
OUT
during iAMT. No 50ohm resistor to GND needed.
True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm series resistor. Free running during
CPUT1_LPR_F
OUT
iAMT No 50 ohm resistor to GND needed.
GNDCPU
PWR Ground pin for the CPU outputs
Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm series resistor. No 50 ohm
CPUC0_LPR
OUT
resistor to GND needed.
True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm series resistor. No 50 ohm resistor to
CPUT0_LPR
OUT
GND needed.
VDDCPU
CK_PWRGD/PD#
FSLB/TEST_MODE
GNDREF
X2
X1
VDDREF
REF0/FSLC/TEST_SEL
SDATA
SCLK
PWR Supply for CPU clocks, 3.3V nominal
Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values.
IN TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test
Clarification Table.
PWR Ground pin for the REF outputs.
OUT Crystal output, Nominally 14.318MHz
IN
Crystal input, Nominally 14.318MHz.
PWR Ref, XTAL power supply, nominal 3.3V
14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for
I/O
Vil_FS and Vih_FS values. /TEST_Sel: 3-level latched input to enable test mode. Refer to Test Clarification Table
I/O Data pin for SMBus circuitry, 3.3V tolerant.
IN
Clock pin of SMBus circuitry, 5V tolerant.
IN
1461A—07/28/09
3
Integrated
Circuit
Systems, Inc.
ICS9LPRS535
Datasheet
General Description
ICS9LPRS535
is compliant to the Intel CK505 Yellow Cover specification. This clock synthesizer provides a single chip
solution for Intel desktop chipsets.
ICS9LPRS535
is driven with a 14.318MHz crystal. It also provides a tight ppm accuracy
output for Serial ATA and PCI-Express support.
Block Diagram
X1
X2
OSC
REF
REF
CPU(1:0)
SRC8/ITP
CPU PLL1
SS
CPU
SRC = SRC_MAIN
SRC(7,5:3)
PCI33MHz
PCI(5:4,0)
PLL3
Non-SS
SE1 (25MHz)
25MHz
SRC2/SATA
FSLA
CKPWRGD/PD#
PCI_STOP#
CPU_STOP#
CR#_(A,C:D)
SRC5_EN
ITP_EN
FSLC/TESTSEL
FSLB/TESTMODE
SRC0/DOT96
Control
Logic
SATA
PLL2
Non-SS
DOT96MHz
48MHz
48MHz
Power Groups
Pin Number
VDD
33
39
30, 21
13
9
6
45
2
1461A—07/28/09
Description
GND
36
36
18, 27
15
12
8
42
5
CPU Outputs
CPU/SRC Analog
SRC Outputs
PLL3 25MHz
DOT96 outputs
USB 48 Output/Analog
Xtal, REF
PCI outputs
4
Integrated
Circuit
Systems, Inc.
Absolute Maximum Ratings - DC Parameters
PARAMETER
Maximum Supply Voltage
Maximum Supply Voltage
Maximum Input Voltage
Minimum Input Voltage
Storage Temperature
Input ESD protection
1
2
3
ICS9LPRS535
Datasheet
SYMBOL
VDDxxx
VDDxxx_IO
V
IH
V
IL
Ts
ESD prot
CONDITIONS
Supply Voltage
Low-Voltage Differential I/O Supply
3.3V Inputs
Any Input
-
Human Body Model
MIN
MAX
4.6
3.8
4.6
150
GND - 0.5
-65
2000
UNITS Notes
V
7
V
7
V
4,5,7
V
4,7
°
4,7
C
V
6,7
Guaranteed by design and characterization, not 100% tested in production.
Operation under these conditions is neither implied, nor guaranteed.
Maximum input voltage is not to exceed VDD
AC Electrical Characteristics - Low Power Differential Outputs
PARAMETER
Rising Edge Slew Rate
Falling Edge Slew Rate
Slew Rate Variation
Differential Voltage Swing
Crossing Point Voltage
Crossing Point Variation
Maximum Output Voltage
Minimum Output Voltage
Duty Cycle
CPU[1:0] Skew
CPU[2_ITP:0] Skew
SRC[10:0] Skew
SYMBOL
tSLR
tFLR
tSLVAR
VSWING
VXABS
VXABSVAR
VHIGH
VLOW
DCYC
CPUSKEW10
CPUSKEW20
SRCSKEW
CONDITIONS
Averaging on
Averaging on
Averaging on
Averaging off
Averaging off
Averaging off
Averaging off
Averaging off
Averaging on
Differential Measurement
Differential Measurement
Differential Measurement
MIN
2.5
2.5
300
300
MAX
4
4
20
550
140
1150
55
100
150
3000
UNITS NOTES
V/ns
2, 3
V/ns
2, 3
%
1, 10
mV
2
mV
1,4,5
mV
1,4,9
mV
1,7
mV
1,8
%
2
ps
1
ps
1
ps
1,6,11
-300
45
NOTES on DIF Output AC Specs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
1
2
3
4
5
6
7
8
9
Measurement taken for single ended waveform on a component test board (not in system)
Measurement taken from differential waveform on a component test board. (not in system)
Slew rate emastured through V_swing voltage range centered about differential zero
Vcross is defined at the voltage where Clock = Clock#, measured on a component test board (not in system)
Only applies to the differential rising edge (Clock rising, Clock# falling)
Total distributed intentional SRC to SRC skew. PCIE Gen2 outputs (SRC3, 4, 6 and 7) will have 0 nominal skew. Maximum allowable interpair skew is 150 ps.
The max voltage including overshoot.
The min voltage including undershoot.
The total variation of all Vcross measurements in any particular system. Note this is a subset of V_cross min/mas (V_Cross absolute) allowed. The intent is to limit Vcross
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising
For PCIe Gen2 compliant devices, SRC 3, 4, 6, and 7 will have 0 ps nominal skew.
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