Low Skew, PCI-X 1-to-4 Fanout Buffer
Datasheet
830584I
G
ENERAL
D
ESCRIPTION
The 830584I is a low skew, general purpose PCI-X 1-to-4 Fanout
Buffer and a member of the family of High Performance Clock Solutions
from IDT. Guaranteed output and part-to-part skew characteristics
make the 830584I ideal for those clock distribution applications
demanding well defined performance and repeatablility. The 830584I
is designed and characterized from -40°C to 85°C for industrial
applications and is packaged in an 8 TSSOP package.
F
EATURES
• General purpose and PCI-X 1:4 clock buffer
• Four single-ended LVCMOS/LVTTL clock outputs
• One single-ended LVCMOS/LVTTL clock input
• Maximum output frequency: 140MHz
• Output enable control (outputs disabled in logic low state)
• Output skew: 100ps (maximum)
• Part-to-part skew: 400ps (maximum)
•
Additive phase jitter, RMS: 0.15ps (typical)
• Space-saving 8 lead TSSOP package
• Full 3.3V operating supply mode
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) packages
B
LOCK
D
IAGRAM
Q0
P
IN
A
SSIGNMENT
CLKIN
OE
Q0
GND
1
2
3
4
8
7
6
5
Q3
Q2
V
DD
Q1
Q1
CLKIN
Q2
830584I
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
Q3
OE
©2015 Integrated Device Technology, Inc
1
December 16, 2015
830584I Datasheet
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3, 5, 7. 8
4
6
Name
CLKIN
OE
Q0, Q1, Q2, Q3
GND
V
DD
Input
Input
Output
Power
Power
Type
Description
Single-ended clock input reference signal.
LVCMOS/LVTTL interface levels.
Output enable control input pin. See Table 3, Function Table.
LVCMOS / LVTTL interface levels.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Power supply ground.
Positive supply pin.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
OUT
Parameter
Input Capacitance
Output Impedance
Test Conditions
Minimum
Typical
4
15
Maximum
Units
pF
Ω
T
ABLE
3. F
UNCTION
T
ABLE
Inputs
OE
0
0
1
1
CLKIN
0
1
0
1
Outputs
Q0:Q3
0
0
0
1
©2015 Integrated Device Technology, Inc
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December 16, 2015
830584I Datasheet
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DD
+ 0.5V
121.5°C/W (0 mps)
-65°C to 150°C
N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
T
ABLE
4A. R
ECOMMENDED
O
PERATING
C
ONDITIONS
,
V
DD
= 3.3V ± 0.3V, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
IH
V
IL
V
I
I
OH
I
OL
T
A
Parameter
Positive Supply Voltage
High Level Input Voltage
Low Level Input Voltage
Input Voltage
High-Level Output Current
Low-Level Output Current
Operating Free-Air Temperature
-40
0
Test Conditions
Minimum
3.0
0.7*V
DD
0.3*V
DD
V
DD
-24
24
85
Typical
3.3
Maximum
3.6
Units
V
V
V
V
mA
mA
°C
T
ABLE
4B. DC C
HARACTERISTICS
,
V
DD
= 3.3V ± 0.3V, T
A
= -40°C
TO
85°C
Symbol
V
IK
V
OH
Parameter
Input Voltage
Output High Voltage
Test Conditions
I
I
= -18mA
I
OH
= -1mA
I
OH
= -24mA
I
OH
= -12mA
I
OL
= 1mA
V
OL
Output Low Voltage
I
OL
= 24mA
I
OL
= 12mA
I
OH
I
OL
I
I
I
DD
C
i
C
o
†
Minimum
V
DD
– 0.2
2
2.4
Typical†
Maximum
–1.2
Units
V
V
V
V
0.2
0.8
0.55
–50
–55
60
70
±150
37
3
3.2
V
V
V
mA
mA
mA
mA
µA
mA
pF
pF
Output High Current
Output Low Current
Input Current
Dynamic Current
Input Capacitance
Output Capacitance
V
O
= 1V
V
O
= 1.65V
V
O
= 2V
V
O
= 1.65V
V
I
= 0V or V
DD
f = 67MHz
V
I
= 0V or V
DD
V
I
= 0V or V
DD
All typical values are at respective nominal V
DD
and 25°C.
©2015 Integrated Device Technology, Inc
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December 16, 2015
830584I Datasheet
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= 3.3V ± 0.3V, T
A
= -40°C
TO
85°C
Symbol
f
clk
tp
LH
tp
HL
tsk(o)
tsk(p)
tsk(pr)
tsk(pp)
tjit
T
high
T
low
t
R
t
F
†
‡
Parameter
Clock Frequency; NOTE 1
Propagation Delay, Low to High;
NOTE 2
Propagation Delay, High to Low;
NOTE 2
Output Skew; NOTE 3, 4
Pulse Skew
Process Skew
Part-to-Part Skew; NOTE 4, 5
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
CLK High Time
CLK Low Time
Output Rise Slew Rate
‡
Output Fall Slew Rate
‡
Test Conditions
Minimum
0
1.8
1.8
Typical
†
Maximum
140
Units
MHz
ns
ns
ps
ps
ps
ps
ps
ns
ns
ns
ns
2.5
2.4
50
3
3
100
170
300
400
140MHz
200
250
140MHz, Integration Range:
10kHz – 20MHz
66MHz
140MHz
66MHz
140MHz
0.2V
DD
to 0.6V
DD
0.6V
DD
to 0.2V
DD
6
3
6
3
1.5
1.5
2.7
2.7
0.15
4
4
V/ns
V/ns
All typical values are at respective nominal V
DD
.
This symbol is according to PCI-X terminology.
NOTE 1: Switching characteristics over recommended ranges of supply voltages and operating free-air temperature,
C
L
= 10pF, V
DD
= 3.3V ± 0.3V.
NOTE 2: Measured from V
DD
/2 of the input to V
DD
/2 of the output.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DD
/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DD
/2.
©2015 Integrated Device Technology, Inc
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December 16, 2015
830584I Datasheet
A
DDITIVE
P
HASE
J
ITTER
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the
dBc Phase
Noise.
This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase
noise is defined as the ratio of the noise power present in a 1Hz
band at a specified offset from the fundamental frequency to the
power value of the fundamental. This ratio is expressed in decibels
(dBm) or a ratio of the power in the 1Hz band to the power in the
fundamental. When the required offset is specified, the phase noise
is called a
dBc
value, which simply means dBm at a specified offset
from the fundamental. By investigating jitter in the frequency domain,
we get a better understanding of its effects on the desired application
over the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
Input/Output Additive Phase Jitter
at
140MHz (12kHz – 20MHz) = 0.15ps typical
SSB P
HASE
N
OISE
dBc/H
Z
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device.
This is illustrated above. The device meets the noise floor of what
is shown, but can actually be lower. The phase noise is dependent
on the input source and measurement equipment.
©2015 Integrated Device Technology, Inc
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December 16, 2015
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