Jitter Attenuator & FemtoClock
®
Multiplier
ICS813252I-02
OBSOLETE
DATA SHEET
G
ENERAL
D
ESCRIPTION
The ICS813252I-02 is a PLL based synchronous multiplier that is
optimized for PDH or SONET to Ethernet clock jitter attenuation
and frequency translation. The device contains two internal
frequency multiplication stages that are cascaded in series. The first
stage is a VCXO PLL that is optimized to provide reference clock
jitter attenuation. The second stage is a FemtoClock
®
frequency
multiplier that provides the low jitter, high frequency Ethernet
output clock that easily meets Gigabit and 10 Gigabit Ethernet jitter
requirements. Pre-divider and output divider multiplication ratios
are selected using device selection control pins. The multiplication
ratios are optimized to support most common clock rates used in
PDH, SONET and Ethernet applications. The VCXO requires the
use of an external, inexpensive pullable crystal. The VCXO uses
external passive loop filter components which allows configuration
of the PLL loop bandwidth and damping characteristics. The
device is packaged in a space-saving 32-VFQFN package and
supports industrial temperature range.
F
EATURES
•
Two LVPECL outputs
Each output supports independent frequency selection at
25MHz, 125MHz, 156.25MHz and 312.5MHz
•
Two differential inputs support the following input types: LVPE-
CL, LVDS, LVHSTL, SSTL, HCSL
•
Accepts input frequencies from 8kHz to 155.52MHz including
8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz,
125MHz and 155.52MHz
•
Attenuates the phase jitter of the input clock by using a low-
cost pullable fundamental mode VCXO crystal
•
VCXO PLL bandwidth can be optimized for jitter attenuation
and reference tracking
using external loop filter connection
•
FemtoClock frequency multiplier provides low jitter, high fre-
quency output
•
Absolute pull range: 50ppm
•
FemtoClock VCO frequency: 625MHz
•
RMS phase jitter @ 125MHz, using a 25MHz crystal
(10kHz – 20MHz): 1.3ps (maximum)
•
3.3V supply voltage
P
IN
A
SSIGNMENT
XTAL_OUT
XTAL_IN
nCLK0
nCLK1
CLK0
CLK1
V
CCX
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
V
CC
ODBSEL_1
ODBSEL_0
ODASEL_1
PDSEL_2
PDSEL_1
PDSEL_0
V
CCA
V
CC
•
-40°C to 85°C ambient operating temperature
•
Available in lead-free (RoHS 6) package
•
For functional replacement device use 813N252CKI-02LF
32 31 30 29 28 27 26 25
LF1
LF0
ISET
V
EE
CLK_SEL
V
CC
RESERVED
V
EE
24
23
22
21
20
19
18
17
V
EE
nQB
QB
V
CCO
nQA
QA
V
EE
ODASEL_0
ICS813252I-02
32-Lead VFQFN
5mm x 5mm x 0.925 package body
K Package
Top View
ICS813252CKI-02 REVISION A AUGUST 4, 2016
1
©2016
Integrated Device Technology, Inc.
ICS813252I-02 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCK
®
MULTIPLIER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3
4, 8, 18, 24
5
6, 12, 27
7
9,
10,
11
13
14,
15
16,
17
19, 20
21
22, 23
25
26
28
29
30,
31
32
Name
LF1, LF0
ISET
V
EE
CLK_SEL
V
CC
RESERVED
PDSEL_2,
PDSEL_1,
PDSEL_0
V
CCA
ODBSEL_1,
ODBSEL_0
ODASEL_1,
ODASEL_0
QA, nQA
V
CCO
QB, nQB
nCLK1
CLK1
nCLK0
CLK0
XTAL_OUT,
XTAL_IN
V
CCX
Type
Analog Input/
Output
Analog Input/
Output
Power
Input
Power
Reserved
Input
Power
Input
Input
Output
Power
Output
Input
Input
Input
Input
Input
Power
Pulldown
Pulldown
Pullup
Pulldown
Description
Loop filter connection node pins.
LF0 is the output. LF1 is the input.
Charge pump current setting pin.
Negative supply pins.
Input clock select. When HIGH selects CLK1/nCLK1.
When LOW, selects CLK0/nCLK0. LVCMOS/LVTTL interface levels.
Core power supply pins.
Reserved pin. Do not connect.
Pre-divider select pins. LVCMOS/LVTTL interface levels.
See Table 3A.
Analog supply pin.
Frequency select pins for Bank B output. See Table 3B. LVCMOS/LVT-
TL interface levels.
Frequency select pins for Bank A output. See Table 3B. LVCMOS/LVT-
TL interface levels.
Differential Bank A clock outputs. LVPECL interface levels.
Output power supply pin.
Differential Bank B clock outputs. LVPECL interface levels.
Pullup/
Inverting differential clock input. V
CC
/2 bias voltage when left floating.
Pulldown
Pulldown Non-inverting differential clock input.
Pullup/
Inverting differential clock input. V
CC
/2 bias voltage when left floating.
Pulldown
Pulldown Non-inverting differential clock input.
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
Power supply pin for VCXO charge pump.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
R
R
PULLUP
PULLDOWN
ICS813252CKI-02 REVISION A AUGUST 4, 2016
3
©2016
Integrated Device Technology, Inc.
FPGA/CPLD
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