November 2009
HI-6120
Parallel Bus Interface and
HI-6121
Serial Peripheral Interface (SPI)
MIL-STD-1553 Remote Terminal ICs
REMOTE TERMINAL FEATURES
·
Fully
integrated 3.3V Remote Terminal meets all
requirements for MIL-STD-1553B Notice 2
receive commands: indexed (single) buffering, ping-
pong (double) buffering and two circular buffer modes
GENERAL DESCRIPTION
The HI-6120 and HI-6121 provide a complete, integrated,
3.3V MIL-STD-1553 Remote Terminal in a monolithic
silicon gate CMOS device. Two host interface options are
offered: The HI-6120 uses a 16-bit parallel host bus
interface for access to registers and RAM and is offered in
a 100-pin plastic quad flat pack (PQFP). The HI-6121 has a
4-wire SPI (Serial Peripheral Interface) host connection
and comes in a reduced pin count 52-pin PQFP or 64-pin
QFN. Both devices handle all aspects of the MIL-STD-
1553 protocol, including message encoding, decoding,
error detection, illegal command detection and data
buffering. Host data management is simplified by storing
message information and data within the on-chip 32K x 16
static RAM.
A descriptor table in shared RAM provides fully
programmable memory management. Multiple descriptor
tables can be implemented for fast context switching.
Transmit and receive commands can use any of four
different data buffer modes: indexed (single) buffering,
ping-pong (double) buffering or two circular buffer
schemes. Transmit and receive commands for each
subaddress may use different buffer modes. Mode code
commands employ a simple scheme for storing mode data
and message information with programmable interrupts.
The device provides internal illegalization capability,
allowing any subset of subaddress, command T/R bit,
broadcast vs non-broadcast and word count (or mode
code) to be illegalized, resulting in a total of 4,096 possible
combinations. The illegalization table resides in internal
RAM. The RT can also operate without illegal command
detection, providing “in form” responses to all valid
commands. Broadcast command recognition is optional.
The HI-6120 and HI-6121 provide programmable
interrupts for automatic message handling, message
status and general status. A host interrupt history log
maintains information about the last 16 interrupts.
The HI-6120 and HI-6121 can be configured for automatic
self-initialization. A dedicated SPI port reads data from
external serial EEPROM memory to fully configure the
descriptor table, illegalization table and host interrupts.
Internal dual-redundant transceivers provide direct
connection to bus isolation transformers. The device is
offered with industrial temperature range. Extended
temperature range is also offered, with optional burn-in. A
“RoHS compliant” lead-free option is offered.
HI-6120 Rev New
·
Four data buffer methods for subaddress transmit and
·
Independently
selectable data buffer modes for
transmit and receive commands on each subaddress
·
Simplified mode code command handling
·
Integral 16-bit Time-Tag counter has programmable
options for clock, interrupts and auto-synchronization
·
Message
information and time-tag words are stored
with message data words for all transacted messages
data from broadcast messages may be optionally
separated from non-broadcast received data
·
In compliance with MIL-STD-1553B Notice 2, received
·
Optional interrupt log buffer stores the most recent 16
interrupts to minimize host service duties
·
Optional illegal command detection uses internal table
·
Optional automatic self-initialization at reset
·
+/- 8kV ESD Protection (HBM, all pins)
·
MIL-STD-1760 compliant
PIN CONFIGURATION (Top View)
HI-6121 in 52-PQFP Package
52 - TXINHB
51 - TXINHA
50 - AUTOEN
49 - VCC
48 - GND
47 - SSYSF
46 - ACTIVE
45 - READY
44 - TTCLK
43 - ACKINT
42 - INTMES
41 - INTHW
40 - BENDI
COMP - 1
CE - 2
MODE - 3
SI - 4
SCK - 5
SO - 6
MCLK - 7
RTA0 - 8
RTA1 - 9
RTA2 - 10
MR - 11
RTA3 - 12
RTA4 - 13
HI-6121PQx
39 - TEST
38 - LOCK
37 - MTSTOFF
36 - BUSA
35 - VCCP
34 - BUSA
33 - BUSB
32 - VCCP
31 - BUSB
30 - TEST0
29 - TEST1
28 - TEST2
27 - TEST3
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RTAP - 14
MISO - 15
MOSI - 16
VCC - 17
GND - 18
ECS - 19
EECOPY - 20
ESCK - 21
EE1K - 22
TEST7 - 23
TEST6 - 24
TEST5 - 25
TEST4 - 26
11/09
HI-6120, HI-6121
BLOCK DIAGRAM
HI-6120 MIL-STD-1553 Terminal With Host Bus Interface
HI-6121 MIL-STD-1553 Terminal With Host SPI Interface
LOCK
EE1K
AUTOEN
EECOPY
MTSTOFF
RTA4 - 0
RTAP
BENDI
BWID
CONFIG.
OPTION
LOGIC
SHARED
STATIC RAM
AND
REGISTERS
32K X 16
ADDRESS
SPACE
LOGIC POWER
VCC
GND
TRANSCEIVER
POWER
VCCP
CONTROL
ADDRESS
BTYPE
WPOL
HI-6120
ONLY
DATA
INTERNAL
CLOCKS
MCLK
TTCLK
(OPT)
R / W or WE
STR or OE
A0 / LB
WAIT or WAIT
A15:1
D15:0
CE
SCK
SI
SO
HOST SPI
INTERFACE
HI-6121
ONLY
HOST BUS
INTERFACE
HI-6120
ONLY
CONTROL
ADDRESS
DATA
MEMORY
ACCESS
MANAGER
TEST
LOGIC
TEST7:0
TEST
MODE
COMP
CONTROL
ADDRESS
DATA
TXINHA
BUSA
ACKHW
ACKMES
}
*
REMOTE
TERMINAL
STATE
MACHINE
MESSAGE
SEQUENCER
AND DUAL
ENCODER-
DECODERS
BUSA
BUS
SSYSF
MR
INTHW
INTMES
READY
ACTIVE
DISCRETE
SIGNAL
INTERFACE
TO HOST
TXINHB
BUSB
BUS
BUSB
BUS
TRANSCEIVERS
*
Combined into ACKINT pin
on HI-6121PQx varient
ESCK
SPI MASTER MODE
INTERFACE
TO OPTIONAL
SERIAL EEPROM
(AUTO-CONFIG)
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MISO
MOSI
ECS
HI-6120, HI-6121
PIN DESCRIPTION
THESE PINS APPLY TO BOTH HI-6120 AND HI-6121
PIN
INTHW
INTMES
MR
MTSTOFF
TYPE
OUTPUT
OUTPUT
INPUT
INPUT
DESCRIPTION
Hardware Interrupt output, active low.This signal is programmed as a brief low-going
pulse output or as a level output by the INTSEL bit in Configuration Register 1.
Message Interrupt output, active low. This signal is programmed as a brief low-going
pulse output or as a level output by the INTSEL bit in Configuration Register 1.
Master Reset, active low.
Internal 50K
W
pull-up resistor.
The host can also assert
software reset by asserting the SRST bit in Configuration Register 1.
Memory test disable, active high.
Internal 50K
W
pull-down resistor.
When this pin is low,
the device performs a memory test on the entire RAM after rising edge on the MR reset
pin. When this pin is high, the RAM test is skipped, resulting in a faster reset process.
For further information, refer to the data sheet section entitled “Reset and Initialization.”
EEPROM Copy, active high.
Internal 50K
W
pull-down resistor. This input is
used to start
the process that copies registers and configuration tables to serial EEPROM. Refer to
the data sheet section entitled “Reset and Initialization.”
Auto-Initialize Enable, active high.
Internal 50K
W
pull-down resistor.
If pin is high at
rising edge on MR reset input, automatic initialization proceeds, copying configuration
data to registers and RAM from an external serial EEPROM via the dedicated auto-
initialization SPl port. Refer to the data sheet section entitled “Reset and Initialization.”
When the AUTOEN pin is high, the EE1K input sets the range of the auto-initialization
process. When EE1K is low, registers and RAM occupying the 32K address range from
0x0 to 0x7FFF are initialized. For applications needing faster initialization, when EE1K is
high, only registers and RAM occupying the 1K address range from 0x0 to 0x03FF are
initialized. This pin has an i
nternal 50K
W
pull-down resistor. If the AUTOEN pin is low,
this pin is not used.
Refer to the data sheet section entitled “Reset and Initialization.”
Remote terminal address bits 4 - 0, and parity bit.
Internal 50K
W
pull-up resistors.
The
RTAP pin should provide odd parity for the address present on pins RTA4:0. Terminal
address and parity pin levels are latched into the Operational Status register when rising
edge occurs on the MR pin. The Operational Status Register value (not these pins)
reflects the active terminal address. The register value can be overwritten by the host
under some circumstances. See Operational Status Register description.
EECOPY
INPUT
AUTOEN
INPUT
EE1K
INPUT
RTA4:0
RTAP
INPUTS
LOCK
INPUT
Internal 50K
W
pull-down resistor. Pin state is latched into the Operational Status register
LOCK bit when rising edge occurs on the
MR
pin.
If Operational Status register LOCK
bit is high, terminal address in the register cannot be overwritten by a host register write.
If Operational Status register LOCK bit is low, the host can overwrite the five terminal
address bits and address parity bit in the Operational Status register.
Transmit Inhibits for Bus A and Bus B, active high.
Internal 50K
W
pull-down resistors.
These inputs are logically ORed with the corresponding TXINHA and TXINHB bits in
Configuration Register 1. If the input pin or register bit is high, bus transmit is disabled.
Pin is low when auto-initialization or built-in test is in-process. Host should not access
shared RAM or device registers when pin state is low. When output is high, the shared
RAM and registers may be configured, and device will begin terminal execution when
the STEX (start execution) bit in Configuration Register 1 is set.
Pin is high when the HI-6120 is actively processing a 1553 command, otherwise low.
Master clock input, 50.0 MHZ ±0.01% (100ppm).
Internal 50K
W
pull-down resistor.
Time-Tag Clock input.
Internal 50K
W
pull-down resistor.
When Configuration Register 1
bits TTCK2:0 = 001, this pin is the clock input for the Time Tag counter. For other values
of TTCK2:0, the Time-Tag counter is internally clocked so the TTCLK pin is not used.
Subsystem fail input, active high.
Internal 50K
W
pull-down resistor.
When this input is
high, the HI-6120 terminal sets the SUBSYS flag in its status word.
Chip select output for the dedicated Serial Peripheral Interface (SPI) that connects to
the optional external serial EEPROM used for automatic self-initialization. For this auto-
initialization SPI, the device operates in SPI master mode while the external memory
operates in slave mode.
This SPI is separate from the host SPI found in the HI-6121.
TXINHA
TXINHB
READY
INPUTS
OUTPUT
ACTIVE
MCLK
TTCLK
OUTPUT
INPUT
INPUT
SSYSF
ECS
INPUT
OUTPUT
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HI-6120, HI-6121
PIN DESCRIPTION, Cont.
THESE PINS APPLY TO BOTH HI-6120 AND HI-6121
PIN
ESCK
MISO
MOSI
BUSA, BUSA
BUSB, BUSB
VCC, VCCP
GND
TEST
TEST7:0
MODE
COMP
CE
TYPE
OUTPUT
INPUT
OUTPUT
ANALOG
ANALOG
POWER
POWER
INPUT
BI-DIR
INPUT
INPUT
INPUT
DESCRIPTION
Serial Clock output signal for the dedicated auto-initialization SPI connected to external
auto-initialization EEPROM.
Serial Input signal (Master-In Slave-Out) for the dedicated auto-initialization SPI
connected to external auto-initialization EEPROM.
Internal 50K
W
pull-down resistor.
Serial Output signal (Master-Out Slave-In) for the dedicated auto-initialization SPI
connected to external auto-initialization EEPROM.
Bi-directional analog interface to MIL-STD-1553 bus A isolation transformer, positive and
negative signals respectively.
Bi-directional analog interface to MIL-STD-1553 bus B isolation transformer, positive and
negative signals respectively.
3.3V supply voltage inputs for logic and transceiver circuits
Ground pin for logic and transceiver circuits
Test enable.
Internal 50K
W
pull-down resistor.
The host asserts this pin to perform RAM
self-test or loopback tests.
Test pins used for factory testing.
Internal 50K
W
pull-down resistor.
Do not connect
these pins.
Test pin used for factory testing.
Internal 50K
W
pull-up resistor.
Do not connect this pin.
Test pin used for factory testing.
Internal 50K
W
pull-down resistor.
Do not connect this
pin.
Chip Enable, active low. Internal 50K
W
pull-up resistor. When asserted, this pin enables
host read or write accesses to device RAM or registers. On HI-6121, it is normally
connected to a host SPI chip select output signal.
Configuration pin for selecting “endianness” of the host bus interface when byte transfers
are used. Internal 50K
W
pull-up resistor. Endianness is the system attribute that
indicates whether integers are represented with the most significant byte stored at the
lowest address (big endian) or at the highest address (little endian). Internal storage is
“big endian.” When using the HI-6120, this pin only applies when the host bus is
configured for 8-bit width, that is, when BWID equals 0. When the HI-6120 is configured
for 16-bit bus width, the BENDI input pin is “don’t care.” When using the HI-6121, this
pin controls the byte order of the 16-bit data following the SPI command.
When BENDI is low, “little endian” is chosen; the low order byte (bits 7:0) is transacted
before the high order byte (bits 15:8). When BENDI is high, “big endian” is chosen and
the high order byte is transacted on the host bus before the low order byte.
B
ENDI
INPUT
ACKHW*
INPUT
Hardware Interrupt Acknowledge, active high.
Internal 50K
W
pull-down resistor. This
input is
only used when the INTSEL bit in Configuration Register 1 is asserted to enable
level interrupts. After interrupt assertion causes the INTHW output to go low, a high
state (60ns minimum duration) on ACKHW will clear the INTHW output to logic 1. The
interrupt is also cleared by reading the Pending Interrupt Register.
Message Interrupt Acknowledge, active high.
Internal 50K
W
pull-down resistor. This input
is
only used when the INTSEL bit in Configuration Register 1 is asserted to enable level
interrupts. After interrupt assertion causes the INTMES output to go low, a high state
(60ns minimum duration) on ACKMES will clear the INTMES output to logic 1. The
interrupt is also cleared by reading the Pending Interrupt Register.
ACKMES*
INPUT
* Note:
These pins are combined into the ACKINT pin on HI-6121PQx variant.
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HI-6120, HI-6121
PIN DESCRIPTION, Cont.
THESE PINS APPLY TO HI-6120 ONLY
PIN
D15:0
TYPE
I/O
DESCRIPTION
Tristate data bus for host read/write operations upon registers and shared RAM.
Internal 50K
W
pull-down resistors.
All read/write operations transact 16 bit words, but
bus width can be configured for 8 or 16 bits. For 8 bit bus width, pins D15:8 are not
connected; each 16-bit word is transacted as a pair of upper and lower byte operations,
with data presented sequentially on pins D7:0. For compatibility with different host
processors, when byte transfers are enabled the BENDI input pin sets whether the low
order byte is transferred before the high order byte, or vice versa.
Address bus for host read/write operations upon registers and shared RAM. For 16-bit
bus width, address bit A0 (LB) from the host is not used. For 8-bit bus width, bit A0
equals 0 during the first byte read/write access; while A0 equals 1 during the second
byte access.
Configuration pin for host bus width.
Internal 50K
W
pull-up resistor. High selects 16-bit
bus width, low selects 8-bit bus width.
Configuration pin for host bus read/write control signal style. Internal 50K
W
pull-up
resistor. High selects “Intel style” using separate read strobe OE (output enable) and
write strobe WE. Low selects “Motorola style” using single read/write strobe STR and
read/write select signal, R/W.
A15:1 and
A0 (LB)
INPUTS
BWID
INPUT
BTYPE
INPUT
R/W or WE
INPUT
R/W (read/write) signal when BTYPE pin is low, or WE (write enable) when BTYPE pin
is high. Internal 50K
W
pull-up resistor. Used for host read or write accesses to device
RAM or registers. Important: This pin or the CE pin should be high during all address
transitions.
Common STR (read/write strobe) when BTYPE pin is low, or
OE (output enable) when
BTYPE pin is high. Internal 50K
W
pull-up resistor. Used for host read or write accesses
to device RAM or registers.
STR or OE
INPUT
WAIT or WAIT
OUTPUT
Host bus read cycle “wait” output. For
compatibility with different host processors, this
output can be made active high or active low, set by the state of the WPOL input pin.
The WAIT output may be ignored when the host processor’s read cycle time is
sufficiently slow to meet worst case (slowest) read cycle timing for this device, or when
wait cycles have been enabled from the processor. The WAIT output is useful when the
host processor runs at high clock rates and/or when processor read wait states do not
provide adequate timing margin for worst case (slowest) read cycle timing for this
device.
Configuration pin for WAIT output polarity.
Internal 50K
W
pull-up resistor. When WPOL
is low, the “wait” output is active low (WAIT). When WPOL is high, the “wait” output is
active high (WAIT). A multiple word sequential read will always assert WAIT during the
first read cycle. As long as successive reads are sequential, no further wait output
occurs.
WPOL
INPUT
THESE PINS APPLY TO HI-6121 ONLY
PIN
SO
TYPE
OUTPUT
DESCRIPTION
Serial Peripheral Interface (SPI) Serial Output pin. SO is normally connected to MISO
(Master In - Slave Out) pin on host SPI port. The SO pin is tri-stated when not
transmitting serial data to host.
Serial Peripheral Interface (SPI) Serial Input pin.
Internal 50K
W
pull-down resistor.
SI is
normally connected to MOSI
(Master Out - Slave In) pin on host SPI port.
Serial Peripheral Interface (SPI) Serial Clock pin.
Internal 50K
W
pull-down resistor.
SCK is normally connected to SCK output pin on host SPI port
Interrupt Acknowledge, active high.
Internal 50K
W
pull-down resistor. This input is
only
used when the INTSEL bit in Configuration Register 1 is asserted to enable level
interrupts. After interrupt assertion causes the INTHW or INTMES output to go low, a
high state (60ns minimum duration) on ACKINT will clear the INTHW or INTMES output
to logic 1. Interrupt are also cleared by reading the Pending Interrupt Register.
SI
INPUT
SCK
.
ACKINT
(HI-6121PQx
variant only)
INPUT
INPUT
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