ADVANCE D COM P ON E NTS PACKAG I NG
512 Megabit Narrow Rail SDRAM
DPSD128MX4WNY5
DESCRIPTION:
The Memory Stack™ series is a family of interchangeable memory devices. The 512 Megabit SDRAM Narrow Rail assembly
utilizes the space saving LP-Stack™ technology to increase memory density. This stack is constructed with two 256Mb
(64M x 4) SDRAMs.
This 512Mb LP-Stack™ has been designed to fit in the
same footprint as the 256Mb (64M x 4) SDRAM TSOPII
monolithic. This stack allows for system upgrade while
providing an alternative low cost memory solution.
PINOUT DIAGRAM
VDD
NC
VDDQ
NC
DQ0
VSSQ
NC
NC
VDDQ
NC
DQ1
VSSQ
NC
VDD
CS1
WE
CAS
RAS
CS0
BA0
BA1
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
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FEATURES:
•
•
Electrical characteristics meet semiconductor
manufacturers’ datasheets
Memory organization:
(2) 256Mb memory devices. Each device arranged
as 64M x 4 bits (16M x 4 bits x 4 banks)
Memory stack organization:
128M x 4 bits (32M x 4 bits x 4 banks)
•
•
•
•
•
JEDEC approved, 2 Rank stack pinout and
footprint (with 2 CSs and 1 CKE)
Optimized for RDIMMs
IPC-A-610, class 2, manufacturing standards
Lead free manufacturing process
Package: 54-Pin TSOPII Narrow Rail stack
•
(TOP VIEW)
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
VSS
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
A0-A12
BA0, BA1
DQ0-DQ3
CAS
RAS
WE
DQM
CKE
CLK
CS0 - CS1
V
DD/
V
SS
V
DDQ/
V
SSQ
NC
30A215-01
REV. F 6/03
Bank Select Address
Data In/Data Out
Column Address Strobe
Row Address Strobe
Data Write Enable
Data Input/Output Mask
Clock Enables
System Clock
Chip Selects
Power Supply/Ground
Data Output Power/Ground
No Connect
CS1
CS0
RAS
CAS
WE
CLK
DQM
CKE
A0-A12
BA0,BA1
(16M x 4bit x 4 bank)
256 Mb SDRAM
(16M x 4 bit x 4 bank)
PIN NAMES
Row Address:
Column Address:
FUNCTIONAL BLOCK DIAGRAM
A0-A12
A0-A9, A11
DQ0-DQ3
This document contains information on a product under consideration for development at DPAC Technologies Corp.
DPAC reserves the right to change or discontinue information on this product without prior notice.
1
512 Megabit Narrow Rail SDRAM
ORDERING INFORMATION
DPSD128MX4WNY5
DP
PREFIX
SD 128M
TYPE MEMORY
DEPTH
X
4
W
DESIG
NY5 - DP - XX
PACKAGE
SUPPLIER
X
XXX
DESIG MEMORY
WIDTH
MFR ID MEMORY CYCLE
REVISION TIME
P12
P13
12
10
08
75
75P2
70
70P2
60
55
BLANK
n
PC100 / CL2
PC100 / CL3
12ns (83MHz)
10ns (100MHz)
8ns (125MHz)
7.5ns (133MHz) CL3
7.5ns (133MHz) CL2
7ns (143MHz) CL3
7ns (133MHz) CL2
6ns (166MHz) CL2
5.5ns (183MHz) CL3
REVISION NOT SPECIFIED
PER MANUFACTURER DIE REVISION
MANUFACTURER CODE *
SUPPLIER CODE *
STACKABLE TSOP WITH NARROW RAILS
256 MEGABIT LVTTL BASED
MODULE WITHOUT SUPPORT LOGIC
SYNCHRONOUS DRAM
* Contact your sales representative for supplier and manufacturer codes.
NOTE:
1. AC Parameters of base memory are unchanged from device manufacturers’ specifications.
2. DC Parameters may be affected by stacking. Please refer to application note 53A004-00 for further information.
3. For assembly and inspection procedures, refer to application note 53A001-00.
4. Maximum reflow temperature recommendation is 215°C.
MECHANICAL DIAGRAM
PIN 1
INDEX
TOP VIEW
SIDE VIEW
BOTTOM VIEW
.0315 [.80] TYP
.891 MAX.
[22.63 MAX.]
.020 [.51] TYP
.102 MAX. [2.59 MAX]
END VIEW DETAIL
END VIEW
.478
-.002
[
12.19
+.15
]
-.05
COPLANARITY:
.004 [.10] from seating plane
Inch [mm]
.463 [11.76] TYP
Lead Toe-to-Toe per device datasheet
+.006
30A215-01
REV. F 6/03
DPAC Technologies
Products & Services for the Integration Age
7321 Lincoln Way, Garden Grove, CA 92841
Tel
714 898 0007
Fax
714 897 1772
www.dpactech.com Nasdaq: DPAC
2
©2003 DPAC Technologies, all rights reserved. DPAC Technologies™, Memory Stack™, System Stack™, LP-Stack™, CS-Stack™ are trademarks of DPAC Technologies Corp.
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